cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: k1 Date: 1- 8-2022, 7:32PM
Device Used: XC9572-15-PC84
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
32 /72 ( 44%) 131 /360 ( 36%) 69 /144 ( 48%) 28 /72 ( 39%) 26 /69 ( 38%)
** Function Block Resources **
Function Mcells FB Inps Signals Pterms IO
Block Used/Tot Used/Tot Used Used/Tot Used/Tot
FB1 16/18 24/36 24 52/90 15/18
FB2 10/18 16/36 16 66/90 1/17
FB3 6/18 29/36 29 13/90 4/17
FB4 0/18 0/36 0 0/90 0/17
----- ----- ----- -----
32/72 69/144 131/360 20/69
* - Resource is exhausted
** Global Control Resources **
The complement of 'CLK' mapped onto global clock net GCK1.
Signal 'GTS1' mapped onto global output enable net GTS1.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 4 4 | I/O : 24 63
Output : 20 20 | GCK/IO : 1 3
Bidirectional : 0 0 | GTS/IO : 1 2
GCK : 1 1 | GSR/IO : 0 1
GTS : 1 1 |
GSR : 0 0 |
---- ----
Total 26 26
** Power Data **
There are 32 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'k1.ise'.
************************* Summary of Mapped Logic ************************
** 20 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
LED<3> 3 7 FB1_1 4 I/O O STD FAST RESET
LED<0> 3 4 FB1_2 1 I/O O STD FAST RESET
LED<5> 3 9 FB1_3 6 I/O O STD FAST RESET
LED<6> 3 10 FB1_4 7 I/O O STD FAST RESET
LED<1> 3 5 FB1_5 2 I/O O STD FAST RESET
LED<2> 3 6 FB1_6 3 I/O O STD FAST RESET
LED<8> 3 12 FB1_7 11 I/O O STD FAST RESET
LED<4> 3 8 FB1_8 5 I/O O STD FAST RESET
LED<10> 3 14 FB1_10 13 I/O O STD FAST RESET
LED<14> 3 18 FB1_12 18 I/O O STD FAST RESET
LED<7> 3 11 FB1_13 20 I/O O STD FAST RESET
LED<11> 3 15 FB1_15 14 I/O O STD FAST RESET
LED<9> 3 13 FB1_16 23 I/O O STD FAST RESET
LED<12> 3 16 FB1_17 15 I/O O STD FAST RESET
SCLK 5 6 FB1_18 24 I/O O STD FAST
SCLKI 5 6 FB2_1 63 I/O O STD FAST
LED<13> 3 17 FB3_2 17 I/O O STD FAST RESET
LED<15> 3 19 FB3_5 19 I/O O STD FAST RESET
MCLK 2 3 FB3_7 35 I/O O STD FAST RESET
DACLK 1 1 FB3_8 21 I/O O STD FAST
** 12 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
count<9>/count<9>_CLKF 5 6 FB1_14 STD
ADC_div<7> 5 14 FB2_7 STD RESET
ADC_div<0> 2 13 FB2_8 STD SET
ADC_div<8> 6 14 FB2_9 STD RESET
ADC_div<1> 5 14 FB2_10 STD SET
ADC_div<3> 8 14 FB2_11 STD SET
ADC_div<6> 7 14 FB2_12 STD RESET
ADC_div<2> 8 14 FB2_15 STD SET
ADC_div<5> 10 14 FB2_17 STD RESET
ADC_div<4> 10 14 FB2_18 STD RESET
count<0> 2 3 FB3_17 STD RESET
ADCClk 2 10 FB3_18 STD RESET
** 6 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
CLK FB1_9 9 GCK/I/O GCK/I
GTS1 FB2_7 76 GTS/I/O GTS/I
ClkSel<0> FB3_1 25 I/O I
ClkSel<1> FB3_3 31 I/O I
ClkSel<2> FB3_4 32 I/O I
ClkSel<3> FB3_6 34 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs
Used due to wire-ANDing in the switch matrix.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 24/12
Number of signals used by logic mapping into function block: 24
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
LED<3> 3 0 0 2 FB1_1 4 I/O O
LED<0> 3 0 0 2 FB1_2 1 I/O O
LED<5> 3 0 0 2 FB1_3 6 I/O O
LED<6> 3 0 0 2 FB1_4 7 I/O O
LED<1> 3 0 0 2 FB1_5 2 I/O O
LED<2> 3 0 0 2 FB1_6 3 I/O O
LED<8> 3 0 0 2 FB1_7 11 I/O O
LED<4> 3 0 0 2 FB1_8 5 I/O O
(unused) 0 0 0 5 FB1_9 9 GCK/I/O GCK/I
LED<10> 3 0 0 2 FB1_10 13 I/O O
(unused) 0 0 0 5 FB1_11 10 GCK/I/O
LED<14> 3 0 0 2 FB1_12 18 I/O O
LED<7> 3 0 0 2 FB1_13 20 I/O O
count<9>/count<9>_CLKF
5 0 0 0 FB1_14 12 GCK/I/O (b)
LED<11> 3 0 0 2 FB1_15 14 I/O O
LED<9> 3 0 0 2 FB1_16 23 I/O O
LED<12> 3 0 0 2 FB1_17 15 I/O O
SCLK 5 0 0 0 FB1_18 24 I/O O
Signals Used by Logic in Function Block
1: ADCClk 9: count<0> 17: count<3>.LFBK
2: CLK 10: count<10>.LFBK 18: count<4>.LFBK
3: ClkSel<0> 11: count<11>.LFBK 19: count<5>.LFBK
4: ClkSel<1> 12: count<12>.LFBK 20: count<6>.LFBK
5: ClkSel<2> 13: count<13>.LFBK 21: count<7>.LFBK
6: ClkSel<3> 14: count<15>.LFBK 22: count<8>.LFBK
7: GTS1 15: count<1>.LFBK 23: count<9>.LFBK
8: LED<13> 16: count<2>.LFBK 24: count<9>/count<9>_CLKF.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
LED<3> ......X.X.....XXXX.....X................ 7 7
LED<0> ......X.X.....X........X................ 4 4
LED<5> ......X.X.....XXXXXX...X................ 9 9
LED<6> ......X.X.....XXXXXXX..X................ 10 10
LED<1> ......X.X.....XX.......X................ 5 5
LED<2> ......X.X.....XXX......X................ 6 6
LED<8> ......X.X.....XXXXXXXXXX................ 12 12
LED<4> ......X.X.....XXXXX....X................ 8 8
LED<10> ......X.XXX...XXXXXXXXXX................ 14 14
LED<14> ......XXXXXXXXXXXXXXXXXX................ 18 18
LED<7> ......X.X.....XXXXXXXX.X................ 11 11
count<9>/count<9>_CLKF
XXXXXX.................................. 6 6
LED<11> ......X.XXXX..XXXXXXXXXX................ 15 15
LED<9> ......X.XX....XXXXXXXXXX................ 13 13
LED<12> ......X.XXXXX.XXXXXXXXXX................ 16 16
SCLK XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 16/20
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
SCLKI 5 5<- /\5 0 FB2_1 63 I/O O
(unused) 0 0 /\5 0 FB2_2 69 I/O (b)
(unused) 0 0 0 5 FB2_3 67 I/O
(unused) 0 0 0 5 FB2_4 68 I/O
(unused) 0 0 0 5 FB2_5 70 I/O
(unused) 0 0 0 5 FB2_6 71 I/O
ADC_div<7> 5 0 0 0 FB2_7 76 GTS/I/O GTS/I
ADC_div<0> 2 0 \/1 2 FB2_8 72 I/O (b)
ADC_div<8> 6 1<- 0 0 FB2_9 74 GSR/I/O (b)
ADC_div<1> 5 0 0 0 FB2_10 75 I/O (b)
ADC_div<3> 8 3<- 0 0 FB2_11 77 GTS/I/O (b)
ADC_div<6> 7 5<- /\3 0 FB2_12 79 I/O (b)
(unused) 0 0 /\5 0 FB2_13 80 I/O (b)
(unused) 0 0 \/3 2 FB2_14 81 I/O (b)
ADC_div<2> 8 3<- 0 0 FB2_15 83 I/O (b)
(unused) 0 0 \/5 0 FB2_16 82 I/O (b)
ADC_div<5> 10 5<- 0 0 FB2_17 84 I/O (b)
ADC_div<4> 10 5<- 0 0 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: ADCClk 7: ADC_div<5>.LFBK 12: ClkSel<0>
2: ADC_div<0>.LFBK 8: ADC_div<6>.LFBK 13: ClkSel<1>
3: ADC_div<1>.LFBK 9: ADC_div<7>.LFBK 14: ClkSel<2>
4: ADC_div<2>.LFBK 10: ADC_div<8>.LFBK 15: ClkSel<3>
5: ADC_div<3>.LFBK 11: CLK 16: GTS1
6: ADC_div<4>.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
SCLKI X.........XXXXX......................... 6 6
ADC_div<7> .XXXXXXXXX.XXXXX........................ 14 14
ADC_div<0> .XXXXXXXXX.X.XXX........................ 13 13
ADC_div<8> .XXXXXXXXX.XXXXX........................ 14 14
ADC_div<1> .XXXXXXXXX.XXXXX........................ 14 14
ADC_div<3> .XXXXXXXXX.XXXXX........................ 14 14
ADC_div<6> .XXXXXXXXX.XXXXX........................ 14 14
ADC_div<2> .XXXXXXXXX.XXXXX........................ 14 14
ADC_div<5> .XXXXXXXXX.XXXXX........................ 14 14
ADC_div<4> .XXXXXXXXX.XXXXX........................ 14 14
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 29/7
Number of signals used by logic mapping into function block: 29
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 25 I/O I
LED<13> 3 0 0 2 FB3_2 17 I/O O
(unused) 0 0 0 5 FB3_3 31 I/O I
(unused) 0 0 0 5 FB3_4 32 I/O I
LED<15> 3 0 0 2 FB3_5 19 I/O O
(unused) 0 0 0 5 FB3_6 34 I/O I
MCLK 2 0 0 3 FB3_7 35 I/O O
DACLK 1 0 0 4 FB3_8 21 I/O O
(unused) 0 0 0 5 FB3_9 26 I/O
(unused) 0 0 0 5 FB3_10 40 I/O
(unused) 0 0 0 5 FB3_11 33 I/O
(unused) 0 0 0 5 FB3_12 41 I/O
(unused) 0 0 0 5 FB3_13 43 I/O
(unused) 0 0 0 5 FB3_14 36 I/O
(unused) 0 0 0 5 FB3_15 37 I/O
(unused) 0 0 0 5 FB3_16 45 I/O
count<0> 2 0 0 3 FB3_17 39 I/O (b)
ADCClk 2 0 0 3 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: ADC_div<0> 11: LED<0> 21: LED<6>
2: ADC_div<1> 12: LED<10> 22: LED<7>
3: ADC_div<2> 13: LED<11> 23: LED<8>
4: ADC_div<3> 14: LED<12> 24: LED<9>
5: ADC_div<4> 15: LED<14> 25: count2_0_0.LFBK
6: ADC_div<5> 16: LED<1> 26: count<0>.LFBK
7: ADC_div<6> 17: LED<2> 27: count<14>.LFBK
8: ADC_div<7> 18: LED<3> 28: count<16>.LFBK
9: ADC_div<8> 19: LED<4> 29: count<9>/count<9>_CLKF
10: GTS1 20: LED<5>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
LED<13> .........XXXXX.XXXXXXXXX.XX.X........... 17 17
LED<15> .........XXXXXXXXXXXXXXX.XXXX........... 19 19
MCLK .........X..............X...X........... 3 3
DACLK ........................X............... 1 1
count<0> .........X...............X..X........... 3 3
ADCClk XXXXXXXXXX.............................. 10 10
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB4_1 46 I/O
(unused) 0 0 0 5 FB4_2 44 I/O
(unused) 0 0 0 5 FB4_3 51 I/O
(unused) 0 0 0 5 FB4_4 52 I/O
(unused) 0 0 0 5 FB4_5 47 I/O
(unused) 0 0 0 5 FB4_6 54 I/O
(unused) 0 0 0 5 FB4_7 55 I/O
(unused) 0 0 0 5 FB4_8 48 I/O
(unused) 0 0 0 5 FB4_9 50 I/O
(unused) 0 0 0 5 FB4_10 57 I/O
(unused) 0 0 0 5 FB4_11 53 I/O
(unused) 0 0 0 5 FB4_12 58 I/O
(unused) 0 0 0 5 FB4_13 61 I/O
(unused) 0 0 0 5 FB4_14 56 I/O
(unused) 0 0 0 5 FB4_15 65 I/O
(unused) 0 0 0 5 FB4_16 62 I/O
(unused) 0 0 0 5 FB4_17 66 I/O
(unused) 0 0 0 5 FB4_18 (b)
******************************* Equations ********************************
********** Mapped Logic **********
FTCPE_ADCClk: FTCPE port map (ADCClk,ADCClk_T,NOT CLK,NOT GTS1,'0');
ADCClk_T <= (NOT ADC_div(0) AND NOT ADC_div(1) AND NOT ADC_div(2) AND
NOT ADC_div(3) AND NOT ADC_div(4) AND NOT ADC_div(5) AND NOT ADC_div(6) AND
NOT ADC_div(7) AND NOT ADC_div(8));
FTCPE_ADC_div0: FTCPE port map (ADC_div(0),ADC_div_T(0),NOT CLK,'0',NOT GTS1);
ADC_div_T(0) <= (NOT ClkSel(3) AND NOT ClkSel(2) AND ClkSel(0) AND
NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND
NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK);
FTCPE_ADC_div1: FTCPE port map (ADC_div(1),ADC_div_T(1),NOT CLK,NOT GTS1,'0');
ADC_div_T(1) <= ((ADC_div(0).LFBK)
OR (NOT ClkSel(3) AND ClkSel(2) AND NOT ClkSel(0) AND
NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
OR (NOT ClkSel(3) AND NOT ClkSel(2) AND ClkSel(0) AND
NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
OR (NOT ClkSel(3) AND ClkSel(1) AND NOT ClkSel(0) AND
NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK));
FTCPE_ADC_div2: FTCPE port map (ADC_div(2),ADC_div_T(2),NOT CLK,NOT GTS1,'0');
ADC_div_T(2) <= ((ClkSel(2) AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
OR (ClkSel(3) AND ClkSel(1) AND NOT ADC_div(2).LFBK AND
NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
OR (ClkSel(1) AND NOT ClkSel(0) AND NOT ADC_div(2).LFBK AND
NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
OR (ADC_div(0).LFBK)
OR (ADC_div(1).LFBK)
OR (NOT ClkSel(3) AND NOT ClkSel(1) AND NOT ADC_div(2).LFBK AND
NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
OR (NOT ClkSel(1) AND ClkSel(0) AND NOT ADC_div(2).LFBK AND
NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK));
FTCPE_ADC_div3: FTCPE port map (ADC_div(3),ADC_div_T(3),NOT CLK,'0',NOT GTS1);
ADC_div_T(3) <= ((ClkSel(3) AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
NOT ADC_div(8).LFBK)
OR (NOT ClkSel(2) AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
NOT ADC_div(8).LFBK)
OR (ClkSel(1) AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
NOT ADC_div(8).LFBK)
OR (ADC_div(0).LFBK)
OR (ADC_div(1).LFBK)
OR (ADC_div(2).LFBK)
OR (ClkSel(0) AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
NOT ADC_div(8).LFBK));
FTCPE_ADC_div4: FTCPE port map (ADC_div(4),ADC_div_T(4),NOT CLK,NOT GTS1,'0');
ADC_div_T(4) <= ((NOT ClkSel(3) AND NOT ClkSel(2) AND ClkSel(1) AND
NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
OR (NOT ClkSel(3) AND NOT ClkSel(2) AND ClkSel(0) AND
NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
OR (NOT ClkSel(3) AND ClkSel(1) AND ClkSel(0) AND
NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
OR (ClkSel(3) AND NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
OR (NOT ClkSel(3) AND ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
OR (ADC_div(0).LFBK)
OR (ADC_div(1).LFBK)
OR (ADC_div(2).LFBK)
OR (ADC_div(3).LFBK));
FTCPE_ADC_div5: FTCPE port map (ADC_div(5),ADC_div_T(5),NOT CLK,NOT GTS1,'0');
ADC_div_T(5) <= ((ADC_div(4).LFBK)
OR (NOT ClkSel(3) AND ClkSel(2) AND NOT ClkSel(1) AND
NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
NOT ADC_div(8).LFBK)
OR (NOT ClkSel(3) AND NOT ClkSel(2) AND ClkSel(1) AND
NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
NOT ADC_div(8).LFBK)
OR (NOT ClkSel(3) AND NOT ClkSel(2) AND ClkSel(0) AND
NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
NOT ADC_div(8).LFBK)
OR (ClkSel(3) AND NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
NOT ADC_div(8).LFBK)
OR (ADC_div(0).LFBK)
OR (ADC_div(1).LFBK)
OR (ADC_div(2).LFBK)
OR (ADC_div(3).LFBK));
FTCPE_ADC_div6: FTCPE port map (ADC_div(6),ADC_div_T(6),NOT CLK,NOT GTS1,'0');
ADC_div_T(6) <= ((ClkSel(3) AND NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
NOT ADC_div(5).LFBK)
OR (NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
NOT ADC_div(5).LFBK AND ADC_div(6).LFBK)
OR (NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
NOT ADC_div(5).LFBK AND ADC_div(8).LFBK)
OR (ClkSel(2) AND ClkSel(1) AND ClkSel(0) AND
NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND
NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK)
OR (NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND
NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK)
OR (NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
NOT ADC_div(5).LFBK AND ADC_div(7).LFBK));
FTCPE_ADC_div7: FTCPE port map (ADC_div(7),ADC_div_T(7),NOT CLK,NOT GTS1,'0');
ADC_div_T(7) <= ((ClkSel(3) AND NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK)
OR (NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND ADC_div(7).LFBK)
OR (NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND ADC_div(8).LFBK)
OR (NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND
NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
NOT ADC_div(6).LFBK));
FTCPE_ADC_div8: FTCPE port map (ADC_div(8),ADC_div_T(8),NOT CLK,NOT GTS1,'0');
ADC_div_T(8) <= ((NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
ADC_div(8).LFBK)
OR (ClkSel(3) AND ClkSel(2) AND NOT ADC_div(0).LFBK AND
NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
NOT ADC_div(7).LFBK)
OR (ClkSel(3) AND ClkSel(1) AND NOT ADC_div(0).LFBK AND
NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
NOT ADC_div(7).LFBK)
OR (ClkSel(3) AND ClkSel(0) AND NOT ADC_div(0).LFBK AND
NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
NOT ADC_div(7).LFBK)
OR (NOT ClkSel(3) AND NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND
NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK));
DACLK_I <= count2_0_0.LFBK;
DACLK <= DACLK_I when GTS1 = '1' else 'Z';
FDCPE_LED0: FDCPE port map (LED_I(0),LED(0),count(9)/count(9)_CLKF.LFBK,'0','0');
LED(0) <= ((GTS1 AND count(0) AND NOT count(1).LFBK)
OR (GTS1 AND NOT count(0) AND count(1).LFBK));
LED(0) <= LED_I(0) when GTS1 = '1' else 'Z';
FTCPE_LED1: FTCPE port map (LED_I(1),LED_T(1),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(1) <= ((NOT GTS1 AND count(2).LFBK)
OR (GTS1 AND count(0) AND count(1).LFBK));
LED(1) <= LED_I(1) when GTS1 = '1' else 'Z';
FTCPE_LED2: FTCPE port map (LED_I(2),LED_T(2),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(2) <= ((NOT GTS1 AND count(3).LFBK)
OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK));
LED(2) <= LED_I(2) when GTS1 = '1' else 'Z';
FTCPE_LED3: FTCPE port map (LED_I(3),LED_T(3),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(3) <= ((NOT GTS1 AND count(4).LFBK)
OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
count(3).LFBK));
LED(3) <= LED_I(3) when GTS1 = '1' else 'Z';
FTCPE_LED4: FTCPE port map (LED_I(4),LED_T(4),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(4) <= ((NOT GTS1 AND count(5).LFBK)
OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
count(3).LFBK AND count(4).LFBK));
LED(4) <= LED_I(4) when GTS1 = '1' else 'Z';
FTCPE_LED5: FTCPE port map (LED_I(5),LED_T(5),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(5) <= ((NOT GTS1 AND count(6).LFBK)
OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
count(3).LFBK AND count(4).LFBK AND count(5).LFBK));
LED(5) <= LED_I(5) when GTS1 = '1' else 'Z';
FTCPE_LED6: FTCPE port map (LED_I(6),LED_T(6),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(6) <= ((NOT GTS1 AND count(7).LFBK)
OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK));
LED(6) <= LED_I(6) when GTS1 = '1' else 'Z';
FTCPE_LED7: FTCPE port map (LED_I(7),LED_T(7),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(7) <= ((NOT GTS1 AND count(8).LFBK)
OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK AND
count(7).LFBK));
LED(7) <= LED_I(7) when GTS1 = '1' else 'Z';
FTCPE_LED8: FTCPE port map (LED_I(8),LED_T(8),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(8) <= ((NOT GTS1 AND count(9).LFBK)
OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK AND
count(7).LFBK AND count(8).LFBK));
LED(8) <= LED_I(8) when GTS1 = '1' else 'Z';
FTCPE_LED9: FTCPE port map (LED_I(9),LED_T(9),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(9) <= ((NOT GTS1 AND count(10).LFBK)
OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK AND
count(7).LFBK AND count(8).LFBK AND count(9).LFBK));
LED(9) <= LED_I(9) when GTS1 = '1' else 'Z';
FTCPE_LED10: FTCPE port map (LED_I(10),LED_T(10),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(10) <= ((NOT GTS1 AND count(11).LFBK)
OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK AND
count(7).LFBK AND count(8).LFBK AND count(9).LFBK AND count(10).LFBK));
LED(10) <= LED_I(10) when GTS1 = '1' else 'Z';
FTCPE_LED11: FTCPE port map (LED_I(11),LED_T(11),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(11) <= ((NOT GTS1 AND count(12).LFBK)
OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK AND
count(7).LFBK AND count(8).LFBK AND count(9).LFBK AND count(10).LFBK AND
count(11).LFBK));
LED(11) <= LED_I(11) when GTS1 = '1' else 'Z';
FTCPE_LED12: FTCPE port map (LED_I(12),LED_T(12),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(12) <= ((NOT GTS1 AND count(13).LFBK)
OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK AND
count(7).LFBK AND count(8).LFBK AND count(9).LFBK AND count(10).LFBK AND
count(11).LFBK AND count(12).LFBK));
LED(12) <= LED_I(12) when GTS1 = '1' else 'Z';
FTCPE_LED13: FTCPE port map (LED_I(13),LED_T(13),count(9)/count(9)_CLKF,'0','0');
LED_T(13) <= ((NOT GTS1 AND count(14).LFBK)
OR (GTS1 AND LED(9) AND LED(10) AND LED(11) AND LED(12) AND
LED(0) AND LED(1) AND LED(2) AND LED(3) AND LED(4) AND LED(5) AND
LED(6) AND LED(7) AND LED(8) AND count(0).LFBK));
LED(13) <= LED_I(13) when GTS1 = '1' else 'Z';
FTCPE_LED14: FTCPE port map (LED_I(14),LED_T(14),count(9)/count(9)_CLKF.LFBK,'0','0');
LED_T(14) <= ((NOT GTS1 AND count(15).LFBK)
OR (GTS1 AND LED(13) AND count(0) AND count(1).LFBK AND
count(2).LFBK AND count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND
count(6).LFBK AND count(7).LFBK AND count(8).LFBK AND count(9).LFBK AND
count(10).LFBK AND count(11).LFBK AND count(12).LFBK AND count(13).LFBK));
LED(14) <= LED_I(14) when GTS1 = '1' else 'Z';
FTCPE_LED15: FTCPE port map (LED_I(15),LED_T(15),count(9)/count(9)_CLKF,'0','0');
LED_T(15) <= ((NOT GTS1 AND count(16).LFBK)
OR (GTS1 AND LED(9) AND LED(10) AND LED(11) AND LED(12) AND
LED(14) AND LED(0) AND LED(1) AND LED(2) AND LED(3) AND LED(4) AND
LED(5) AND LED(6) AND LED(7) AND LED(8) AND count(0).LFBK AND
count(14).LFBK));
LED(15) <= LED_I(15) when GTS1 = '1' else 'Z';
FDCPE_MCLK: FDCPE port map (MCLK_I,MCLK,count(9)/count(9)_CLKF,'0','0');
MCLK <= (GTS1 AND NOT count2_0_0.LFBK);
MCLK <= MCLK_I when GTS1 = '1' else 'Z';
SCLK <= ((ClkSel(3) AND ADCClk)
OR (ClkSel(2) AND ADCClk)
OR (ClkSel(1) AND ADCClk)
OR (ClkSel(0) AND ADCClk)
OR (NOT ClkSel(3) AND NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
CLK));
SCLKI <= NOT (((ClkSel(3) AND ADCClk)
OR (ClkSel(2) AND ADCClk)
OR (ClkSel(1) AND ADCClk)
OR (ClkSel(0) AND ADCClk)
OR (NOT ClkSel(3) AND NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
CLK)));
FDCPE_count0: FDCPE port map (count(0),count_D(0),count(9)/count(9)_CLKF,'0','0');
count_D(0) <= (GTS1 AND NOT count(0).LFBK);
count(9)/count(9)_CLKF <= ((ClkSel(3) AND ADCClk)
OR (ClkSel(2) AND ADCClk)
OR (ClkSel(1) AND ADCClk)
OR (ClkSel(0) AND ADCClk)
OR (NOT ClkSel(3) AND NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
CLK));
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC9572-15-PC84
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
| 12 74 |
| 13 73 |
| 14 72 |
| 15 71 |
| 16 70 |
| 17 69 |
| 18 68 |
| 19 67 |
| 20 66 |
| 21 XC9572-15-PC84 65 |
| 22 64 |
| 23 63 |
| 24 62 |
| 25 61 |
| 26 60 |
| 27 59 |
| 28 58 |
| 29 57 |
| 30 56 |
| 31 55 |
| 32 54 |
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 LED<0> 43 TIE
2 LED<1> 44 TIE
3 LED<2> 45 TIE
4 LED<3> 46 TIE
5 LED<4> 47 TIE
6 LED<5> 48 TIE
7 LED<6> 49 GND
8 GND 50 TIE
9 CLK 51 TIE
10 TIE 52 TIE
11 LED<8> 53 TIE
12 TIE 54 TIE
13 LED<10> 55 TIE
14 LED<11> 56 TIE
15 LED<12> 57 TIE
16 GND 58 TIE
17 LED<13> 59 TDO
18 LED<14> 60 GND
19 LED<15> 61 TIE
20 LED<7> 62 TIE
21 DACLK 63 SCLKI
22 VCC 64 VCC
23 LED<9> 65 TIE
24 SCLK 66 TIE
25 ClkSel<0> 67 TIE
26 TIE 68 TIE
27 GND 69 TIE
28 TDI 70 TIE
29 TMS 71 TIE
30 TCK 72 TIE
31 ClkSel<1> 73 VCC
32 ClkSel<2> 74 TIE
33 TIE 75 TIE
34 ClkSel<3> 76 GTS1
35 MCLK 77 TIE
36 TIE 78 VCC
37 TIE 79 TIE
38 VCC 80 TIE
39 TIE 81 TIE
40 TIE 82 TIE
41 TIE 83 TIE
42 GND 84 TIE
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572-15-PC84
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25