Equations

********** Mapped Logic **********

FTCPE_ADCClk: FTCPE port map (ADCClk,ADCClk_T,NOT CLK,NOT GTS1,'0');
     ADCClk_T <= (NOT ADC_div(0) AND NOT ADC_div(1) AND NOT ADC_div(2) AND
      NOT ADC_div(3) AND NOT ADC_div(4) AND NOT ADC_div(5) AND NOT ADC_div(6) AND
      NOT ADC_div(7) AND NOT ADC_div(8));

FTCPE_ADC_div0: FTCPE port map (ADC_div(0),ADC_div_T(0),NOT CLK,'0',NOT GTS1);
     ADC_div_T(0) <= (NOT ClkSel(3) AND NOT ClkSel(2) AND ClkSel(0) AND
      NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND
      NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
      NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK);

FTCPE_ADC_div1: FTCPE port map (ADC_div(1),ADC_div_T(1),NOT CLK,NOT GTS1,'0');
     ADC_div_T(1) <= ((ADC_div(0).LFBK)
      OR (NOT ClkSel(3) AND ClkSel(2) AND NOT ClkSel(0) AND
      NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
      NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
      NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
      OR (NOT ClkSel(3) AND NOT ClkSel(2) AND ClkSel(0) AND
      NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
      NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
      NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
      OR (NOT ClkSel(3) AND ClkSel(1) AND NOT ClkSel(0) AND
      NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
      NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
      NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK));

FTCPE_ADC_div2: FTCPE port map (ADC_div(2),ADC_div_T(2),NOT CLK,NOT GTS1,'0');
     ADC_div_T(2) <= ((ClkSel(2) AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
      NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
      NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
      OR (ClkSel(3) AND ClkSel(1) AND NOT ADC_div(2).LFBK AND
      NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
      NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
      OR (ClkSel(1) AND NOT ClkSel(0) AND NOT ADC_div(2).LFBK AND
      NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
      NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
      OR (ADC_div(0).LFBK)
      OR (ADC_div(1).LFBK)
      OR (NOT ClkSel(3) AND NOT ClkSel(1) AND NOT ADC_div(2).LFBK AND
      NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
      NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
      OR (NOT ClkSel(1) AND ClkSel(0) AND NOT ADC_div(2).LFBK AND
      NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
      NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK));

FTCPE_ADC_div3: FTCPE port map (ADC_div(3),ADC_div_T(3),NOT CLK,'0',NOT GTS1);
     ADC_div_T(3) <= ((ClkSel(3) AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
      NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
      NOT ADC_div(8).LFBK)
      OR (NOT ClkSel(2) AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
      NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
      NOT ADC_div(8).LFBK)
      OR (ClkSel(1) AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
      NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
      NOT ADC_div(8).LFBK)
      OR (ADC_div(0).LFBK)
      OR (ADC_div(1).LFBK)
      OR (ADC_div(2).LFBK)
      OR (ClkSel(0) AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
      NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
      NOT ADC_div(8).LFBK));

FTCPE_ADC_div4: FTCPE port map (ADC_div(4),ADC_div_T(4),NOT CLK,NOT GTS1,'0');
     ADC_div_T(4) <= ((NOT ClkSel(3) AND NOT ClkSel(2) AND ClkSel(1) AND
      NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
      NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
      OR (NOT ClkSel(3) AND NOT ClkSel(2) AND ClkSel(0) AND
      NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
      NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
      OR (NOT ClkSel(3) AND ClkSel(1) AND ClkSel(0) AND
      NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
      NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
      OR (ClkSel(3) AND NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
      NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
      NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
      OR (NOT ClkSel(3) AND ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
      NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
      NOT ADC_div(7).LFBK AND NOT ADC_div(8).LFBK)
      OR (ADC_div(0).LFBK)
      OR (ADC_div(1).LFBK)
      OR (ADC_div(2).LFBK)
      OR (ADC_div(3).LFBK));

FTCPE_ADC_div5: FTCPE port map (ADC_div(5),ADC_div_T(5),NOT CLK,NOT GTS1,'0');
     ADC_div_T(5) <= ((ADC_div(4).LFBK)
      OR (NOT ClkSel(3) AND ClkSel(2) AND NOT ClkSel(1) AND
      NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
      NOT ADC_div(8).LFBK)
      OR (NOT ClkSel(3) AND NOT ClkSel(2) AND ClkSel(1) AND
      NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
      NOT ADC_div(8).LFBK)
      OR (NOT ClkSel(3) AND NOT ClkSel(2) AND ClkSel(0) AND
      NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
      NOT ADC_div(8).LFBK)
      OR (ClkSel(3) AND NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
      NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
      NOT ADC_div(8).LFBK)
      OR (ADC_div(0).LFBK)
      OR (ADC_div(1).LFBK)
      OR (ADC_div(2).LFBK)
      OR (ADC_div(3).LFBK));

FTCPE_ADC_div6: FTCPE port map (ADC_div(6),ADC_div_T(6),NOT CLK,NOT GTS1,'0');
     ADC_div_T(6) <= ((ClkSel(3) AND NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
      NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
      NOT ADC_div(5).LFBK)
      OR (NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
      NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
      NOT ADC_div(5).LFBK AND ADC_div(6).LFBK)
      OR (NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
      NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
      NOT ADC_div(5).LFBK AND ADC_div(8).LFBK)
      OR (ClkSel(2) AND ClkSel(1) AND ClkSel(0) AND
      NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND
      NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK)
      OR (NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
      NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND
      NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK)
      OR (NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
      NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
      NOT ADC_div(5).LFBK AND ADC_div(7).LFBK));

FTCPE_ADC_div7: FTCPE port map (ADC_div(7),ADC_div_T(7),NOT CLK,NOT GTS1,'0');
     ADC_div_T(7) <= ((ClkSel(3) AND NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
      NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
      NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK)
      OR (NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
      NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
      NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND ADC_div(7).LFBK)
      OR (NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
      NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
      NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND ADC_div(8).LFBK)
      OR (NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
      NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND
      NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
      NOT ADC_div(6).LFBK));

FTCPE_ADC_div8: FTCPE port map (ADC_div(8),ADC_div_T(8),NOT CLK,NOT GTS1,'0');
     ADC_div_T(8) <= ((NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND
      NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND
      NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK AND
      ADC_div(8).LFBK)
      OR (ClkSel(3) AND ClkSel(2) AND NOT ADC_div(0).LFBK AND
      NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
      NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
      NOT ADC_div(7).LFBK)
      OR (ClkSel(3) AND ClkSel(1) AND NOT ADC_div(0).LFBK AND
      NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
      NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
      NOT ADC_div(7).LFBK)
      OR (ClkSel(3) AND ClkSel(0) AND NOT ADC_div(0).LFBK AND
      NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND NOT ADC_div(3).LFBK AND
      NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND NOT ADC_div(6).LFBK AND
      NOT ADC_div(7).LFBK)
      OR (NOT ClkSel(3) AND NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
      NOT ADC_div(0).LFBK AND NOT ADC_div(1).LFBK AND NOT ADC_div(2).LFBK AND
      NOT ADC_div(3).LFBK AND NOT ADC_div(4).LFBK AND NOT ADC_div(5).LFBK AND
      NOT ADC_div(6).LFBK AND NOT ADC_div(7).LFBK));

DACLK_I <= count2_0_0.LFBK;
DACLK <= DACLK_I when GTS1 = '1' else 'Z';

FDCPE_LED0: FDCPE port map (LED_I(0),LED(0),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED(0) <= ((GTS1 AND count(0) AND NOT count(1).LFBK)
      OR (GTS1 AND NOT count(0) AND count(1).LFBK));
     LED(0) <= LED_I(0) when GTS1 = '1' else 'Z';

FTCPE_LED1: FTCPE port map (LED_I(1),LED_T(1),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(1) <= ((NOT GTS1 AND count(2).LFBK)
      OR (GTS1 AND count(0) AND count(1).LFBK));
     LED(1) <= LED_I(1) when GTS1 = '1' else 'Z';

FTCPE_LED2: FTCPE port map (LED_I(2),LED_T(2),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(2) <= ((NOT GTS1 AND count(3).LFBK)
      OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK));
     LED(2) <= LED_I(2) when GTS1 = '1' else 'Z';

FTCPE_LED3: FTCPE port map (LED_I(3),LED_T(3),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(3) <= ((NOT GTS1 AND count(4).LFBK)
      OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
      count(3).LFBK));
     LED(3) <= LED_I(3) when GTS1 = '1' else 'Z';

FTCPE_LED4: FTCPE port map (LED_I(4),LED_T(4),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(4) <= ((NOT GTS1 AND count(5).LFBK)
      OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
      count(3).LFBK AND count(4).LFBK));
     LED(4) <= LED_I(4) when GTS1 = '1' else 'Z';

FTCPE_LED5: FTCPE port map (LED_I(5),LED_T(5),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(5) <= ((NOT GTS1 AND count(6).LFBK)
      OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
      count(3).LFBK AND count(4).LFBK AND count(5).LFBK));
     LED(5) <= LED_I(5) when GTS1 = '1' else 'Z';

FTCPE_LED6: FTCPE port map (LED_I(6),LED_T(6),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(6) <= ((NOT GTS1 AND count(7).LFBK)
      OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
      count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK));
     LED(6) <= LED_I(6) when GTS1 = '1' else 'Z';

FTCPE_LED7: FTCPE port map (LED_I(7),LED_T(7),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(7) <= ((NOT GTS1 AND count(8).LFBK)
      OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
      count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK AND
      count(7).LFBK));
     LED(7) <= LED_I(7) when GTS1 = '1' else 'Z';

FTCPE_LED8: FTCPE port map (LED_I(8),LED_T(8),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(8) <= ((NOT GTS1 AND count(9).LFBK)
      OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
      count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK AND
      count(7).LFBK AND count(8).LFBK));
     LED(8) <= LED_I(8) when GTS1 = '1' else 'Z';

FTCPE_LED9: FTCPE port map (LED_I(9),LED_T(9),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(9) <= ((NOT GTS1 AND count(10).LFBK)
      OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
      count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK AND
      count(7).LFBK AND count(8).LFBK AND count(9).LFBK));
     LED(9) <= LED_I(9) when GTS1 = '1' else 'Z';

FTCPE_LED10: FTCPE port map (LED_I(10),LED_T(10),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(10) <= ((NOT GTS1 AND count(11).LFBK)
      OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
      count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK AND
      count(7).LFBK AND count(8).LFBK AND count(9).LFBK AND count(10).LFBK));
     LED(10) <= LED_I(10) when GTS1 = '1' else 'Z';

FTCPE_LED11: FTCPE port map (LED_I(11),LED_T(11),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(11) <= ((NOT GTS1 AND count(12).LFBK)
      OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
      count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK AND
      count(7).LFBK AND count(8).LFBK AND count(9).LFBK AND count(10).LFBK AND
      count(11).LFBK));
     LED(11) <= LED_I(11) when GTS1 = '1' else 'Z';

FTCPE_LED12: FTCPE port map (LED_I(12),LED_T(12),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(12) <= ((NOT GTS1 AND count(13).LFBK)
      OR (GTS1 AND count(0) AND count(1).LFBK AND count(2).LFBK AND
      count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND count(6).LFBK AND
      count(7).LFBK AND count(8).LFBK AND count(9).LFBK AND count(10).LFBK AND
      count(11).LFBK AND count(12).LFBK));
     LED(12) <= LED_I(12) when GTS1 = '1' else 'Z';

FTCPE_LED13: FTCPE port map (LED_I(13),LED_T(13),count(9)/count(9)_CLKF,'0','0');
     LED_T(13) <= ((NOT GTS1 AND count(14).LFBK)
      OR (GTS1 AND LED(9) AND LED(10) AND LED(11) AND LED(12) AND
      LED(0) AND LED(1) AND LED(2) AND LED(3) AND LED(4) AND LED(5) AND
      LED(6) AND LED(7) AND LED(8) AND count(0).LFBK));
     LED(13) <= LED_I(13) when GTS1 = '1' else 'Z';

FTCPE_LED14: FTCPE port map (LED_I(14),LED_T(14),count(9)/count(9)_CLKF.LFBK,'0','0');
     LED_T(14) <= ((NOT GTS1 AND count(15).LFBK)
      OR (GTS1 AND LED(13) AND count(0) AND count(1).LFBK AND
      count(2).LFBK AND count(3).LFBK AND count(4).LFBK AND count(5).LFBK AND
      count(6).LFBK AND count(7).LFBK AND count(8).LFBK AND count(9).LFBK AND
      count(10).LFBK AND count(11).LFBK AND count(12).LFBK AND count(13).LFBK));
     LED(14) <= LED_I(14) when GTS1 = '1' else 'Z';

FTCPE_LED15: FTCPE port map (LED_I(15),LED_T(15),count(9)/count(9)_CLKF,'0','0');
     LED_T(15) <= ((NOT GTS1 AND count(16).LFBK)
      OR (GTS1 AND LED(9) AND LED(10) AND LED(11) AND LED(12) AND
      LED(14) AND LED(0) AND LED(1) AND LED(2) AND LED(3) AND LED(4) AND
      LED(5) AND LED(6) AND LED(7) AND LED(8) AND count(0).LFBK AND
      count(14).LFBK));
     LED(15) <= LED_I(15) when GTS1 = '1' else 'Z';

FDCPE_MCLK: FDCPE port map (MCLK_I,MCLK,count(9)/count(9)_CLKF,'0','0');
MCLK <= (GTS1 AND NOT count2_0_0.LFBK);
MCLK <= MCLK_I when GTS1 = '1' else 'Z';

SCLK <= ((ClkSel(3) AND ADCClk)
      OR (ClkSel(2) AND ADCClk)
      OR (ClkSel(1) AND ADCClk)
      OR (ClkSel(0) AND ADCClk)
      OR (NOT ClkSel(3) AND NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
      CLK));

SCLKI <= NOT (((ClkSel(3) AND ADCClk)
      OR (ClkSel(2) AND ADCClk)
      OR (ClkSel(1) AND ADCClk)
      OR (ClkSel(0) AND ADCClk)
      OR (NOT ClkSel(3) AND NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
      CLK)));

FDCPE_count0: FDCPE port map (count(0),count_D(0),count(9)/count(9)_CLKF,'0','0');
count_D(0) <= (GTS1 AND NOT count(0).LFBK);

count(9)/count(9)_CLKF <= ((ClkSel(3) AND ADCClk)
      OR (ClkSel(2) AND ADCClk)
      OR (ClkSel(1) AND ADCClk)
      OR (ClkSel(0) AND ADCClk)
      OR (NOT ClkSel(3) AND NOT ClkSel(2) AND NOT ClkSel(1) AND NOT ClkSel(0) AND
      CLK));