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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:23:07 08/11/2010 
-- Design Name: 
-- Module Name:    clock1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;                                         -- Library declaration
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clock1 is
   Port ( CLK_10M : in std_logic;                    -- 1/200000 counter INPUT
           CLK_50 : out std_logic );                    -- 1/200000 counter OUTPUT
 -- attribute pin_assign : string;                      -- Pin assign
  --attribute pin_assign of S : signal is "6,2";
 -- attribute pin_assign of R : signal is "4,44";
  --attribute pin_assign of Q : signal is "42,40";
  --attribute pin_assign of CLK_10M : signal is "7";
  --attribute pin_assign of CLK_50 : signal is "39";
  --attribute pin_assign of A : signal is "37";
  --attribute pin_assign of B : signal is "35";
  --attribute pin_assign of C : signal is "33";
  --attribute pin_assign of DEC : signal is "27,25,28,26,22,20,18,24";
end clock1;

architecture Behavioral of clock1 is
  signal Q100K : std_logic_vector(16 downto 0);       -- 1/100000 counter
  signal QCLK : std_logic_vector(0 downto 0);         -- 1/2 counter

begin

-- ** 1/200000 counter **
  CLK_50 <= QCLK(0);                                  -- Set OUTPUT
  process( CLK_10M ) begin
    if CLK_10M = '1' and CLK_10M'event then             -- Clock rising edge ?
      if Q100K = 999999 then                             -- Count = 100000 ?
         Q100K <= "00000000000000000";                -- YES. Clear counter
         QCLK <= QCLK + '1';                          -- Set 1/200000 counter
      else                                            -- No.
         Q100K <= Q100K + '1';                        -- Count-up
      end if;
    end if;
  end process;
end Behavioral;

