list b=4 ; * list p=16f59 ; 16F59 #include ; processor specific variable definitions cblock 0x010 Temp1 endc cblock 0x030 Temp2 endc cblock 0x050 Temp3 endc cblock 0x070 Temp4 endc cblock 0x090 Temp5 endc cblock 0x0B0 Temp6 endc cblock 0x0D0 Temp7 endc cblock 0x0F0 Temp8 endc banksel_16F5x macro reg if (reg & 0x80)==0 bcf FSR,7 else bsf FSR,7 endif if (reg & 0x40)==0 bcf FSR,6 else bsf FSR,6 endif if (reg & 0x20)==0 bcf FSR,5 else bsf FSR,5 endif endm org 0x000 Start movlw 0x10 movwf FSR RamClear clrf INDF movlw 0x20 addwf FSR,f btfss STATUS,C goto RamClear banksel_16F5x Temp1 movlw 0x11 movwf Temp1 banksel_16F5x Temp2 movlw 0x33 movwf Temp2 banksel_16F5x Temp3 movlw 0x55 movwf Temp3 banksel_16F5x Temp4 movlw 0x77 movwf Temp4 banksel_16F5x Temp5 movlw 0x99 movwf Temp5 banksel_16F5x Temp6 movlw 0xBB movwf Temp6 banksel_16F5x Temp7 movlw 0xDD movwf Temp7 banksel_16F5x Temp8 movlw 0xFF movwf Temp8 banksel_16F5x Temp1 clrw movf Temp1,w banksel_16F5x Temp2 clrw movf Temp2,w banksel_16F5x Temp3 clrw movf Temp3,w banksel_16F5x Temp4 clrw movf Temp4,w banksel_16F5x Temp5 clrw movf Temp5,w banksel_16F5x Temp6 clrw movf Temp6,w banksel_16F5x Temp7 clrw movf Temp7,w banksel_16F5x Temp8 clrw movf Temp8,w goto $ org 0x7FF goto Start END ; directive 'end of program'