// COnfig Setup
// Configuációk lehetőségek, részletezés: 
//MPLAB_C18_Config_Settings_51537c.pdf tartalmazza a beállításokat

/* 96MHz PLL Prescaler(4MHz-et kíván a bemenetén):
PLLDIV = 1 No divide (4MHz input)
PLLDIV = 2 Divide by 2 (8MHz input)
PLLDIV = 3 Divide by 3 (12MHz input)
PLLDIV = 4 Divide by 4 (16MHz input)
PLLDIV = 5 Divide by 5 (20MHz input)
PLLDIV = 6 Divide by 6 (24MHz input)
PLLDIV = 10 Divide by 10 (40MHz input)
PLLDIV = 12 Divide by 12 (48MHz input)
*/
#pragma config PLLDIV = 5

/* Full-Speed USB Clock Source Selection:
USBDIV = 1 Clock source from OSC1/OSC2
USBDIV = 2 Clock source from 96MHz PLL/2
*/
#pragma config USBDIV = 2

/* Oscillator Selection bits:
FOSC = XT_XT XT oscillator, XT used by USB
FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB
FOSC = ECIO_EC External clock, port function on RA6, EC used by USB
FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB
FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6,EC used by USB
FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB
FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB
FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB
FOSC = INTOSC_XT Internal oscillator, XT used by USB
FOSC = INTOSC_HS Internal oscillator, HS used by USB
FOSC = HS HS oscillator, HS used by USB
FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB
*/
#pragma config FOSC = HSPLL_HS   /*

/* CPU System Clock Postscaler:
CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96MHz PLL Src: /2]
CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96MHz PLL Src: /3]
CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96MHz PLL Src: /4]
CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96MHz PLL Src: /6]
*/
#pragma config CPUDIV = OSC1_PLL2

/* Fail Safe Clock Monitor:
FCMEN = OFF Disabled
FCMEN = ON Enabled
*/
#pragma config FCMEN = OFF

/* Internal/External Switch Over:
IESO = OFF Disabled
IESO = ON Enabled
*/
#pragma config IESO = OFF

/* Power Up Timer:
PWRT = ON Enabled
PWRT = OFF Disabled
*/
#pragma config PWRT = OFF

/* Brown Out Reset:
BOR = OFF Disabled
BOR = SOFT Controlled by SBOREN bit is disabled
BOR = ON_ACTIVE Enabled when the device is not in SLEEP, SBOREN
BOR = ON Enabled, SBOREN bit is disabled
*/
#pragma config BOR = OFF

/* Brown Out Voltage:
BORV = 46 4.6V
BORV = 43 4.3V
BORV = 28 2.8V
BORV = 21 2.1V
*/
//#pragma config BORV = 21

/* USB Voltage Regulator Enable:
VREGEN = OFF Disabled
VREGEN = ON Enabled
*/
#pragma config VREGEN = ON

/* Watchdog Timer:
WDT = OFF HW Disabled - SW Controlled
WDT = ON HW Enabled - SW Disabled
*/
#pragma config WDT = OFF

/* Watchdog Postscaler:
WDTPS = 1 1:1
WDTPS = 2 1:2
WDTPS = 4 1:4
WDTPS = 8 1:8
WDTPS = 16 1:16
WDTPS = 32 1:32
WDTPS = 64 1:64
WDTPS = 128 1:128
WDTPS = 256 1:256
WDTPS = 512 1:512
WDTPS = 1024 1:1024
WDTPS = 2048 1:2048
WDTPS = 4096 1:4096
WDTPS = 8192 1:8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
*/
#pragma config WDTPS = 32768

/* MCLR Enable:
MCLRE = OFF Disabled
MCLRE = ON Enabled
*/
#pragma config MCLRE = ON

/* Low Power Timer1 Oscillator Enable:
LPT1OSC = OFF Timer1 oscillator configured for high power
LPT1OSC = ON Timer1 oscillator configured for low power
*/
#pragma config LPT1OSC = OFF

/* Port B A/D Enable:
PBADEN = OFF PortB<4:0> pins are configured as digital I/O on RESET
PBADEN = ON PortB<4:0> pins are configured as analog input on RESET
*/
#pragma config PBADEN = OFF

/* CCP2 Mux bit:
CCP2MX = OFF CCP2 input/output is multiplexed with RB3
CCP2MX = ON CCP2 input/output is multiplexed with RC1
*/
#pragma config CCP2MX = ON

/* Stack Overflow Reset:
STVREN = OFF Disabled
STVREN = ON Enabled
*/
#pragma config STVREN = ON

/* Low Voltage ICSP:
LVP = OFF Disabled
LVP = ON Enabled
*/
#pragma config LVP = OFF

/* Dedicated In-Circuit Debug/Programming Enable:
ICPRT = OFF Disabled
ICPRT = ON Enabled
*/
//#pragma config ICPRT = OFF

/* Extended Instruction Set Enable:
XINST = OFF Disabled
XINST = ON Enabled
*/
#pragma config XINST = OFF

/* Background Debugger Enable:
DEBUG = ON Enabled
DEBUG = OFF Disabled
*/
#pragma config DEBUG = OFF

/* Boot Block Code Protection:
CPB = ON Enabled
CPB = OFF Disabled
*/
#pragma config CPB = OFF

/* Code Protection Block 0,1,2,3:
CP0 = ON Enabled
CP0 = OFF Disabled
*/
#pragma config CP0 = OFF
#pragma config CP1 = OFF
#pragma config CP2 = OFF
#pragma config CP3 = OFF

/* Data EEPROM Code Protection:
CPD = ON Enabled
CPD = OFF Disabled
*/
#pragma config CPD = OFF

/* Boot Block Write Protection:
WRTB = ON Enabled
WRTB = OFF Disabled
*/
#pragma config WRTB = OFF

/* Write Protection Block 0,1,2,3:
WRT0 = ON Enabled
WRT0 = OFF Disabled
*/
#pragma config WRT0 = OFF
#pragma config WRT1 = OFF
#pragma config WRT2 = OFF
#pragma config WRT3 = OFF

/* Configuration Register Write Protection:
WRTC = ON Enabled
WRTC = OFF Disabled
*/
#pragma config WRTC = OFF

/* Data EEPROM Write Protection:
WRTD = ON Enabled
WRTD = OFF Disabled
*/
#pragma config WRTD = OFF

/* Boot Block Table Read Protection:
EBTRB = ON Enabled
EBTRB = OFF Disabled
*/
#pragma config EBTRB = OFF

/* Table Read Protection Block 0,1,2,3:
EBTR0 = ON Enabled
EBTR0 = OFF Disabled
*/
#pragma config EBTR0 = OFF
#pragma config EBTR1 = OFF
#pragma config EBTR2 = OFF
#pragma config EBTR3 = OFF
/* Configurálás vége */