Low: 11100001
      CKSEL[3:0] Clock source selection
      SUT[1:0] Startup time selection
      CKOUT (0:Output system clock on the CLKO pin)
      CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:11-11101
      BODLEVEL[2:0] (111:Off, 110:1.8, 101:2.7, 100:4.3, 011:2.3, 010:2.2, 001:1.9, 000:2)
      EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
      WDTON (1:WDT normal, 0:WDT always on)
      SPIEN (1:Disable ISP, 0:Enable ISP) *Available only HVS mode
      DWEN (On-Chip Debugging via RESET pin 1:Disable, 0:Enable)
      RSTDISBL (RESET pin 1:Enable, 0:Disable(PORT))

Ext: -------1
             SELFPRGEN *Refer to data sheet

