PIN No.
|
Mark
|
I/O
|
Function
|
1
|
VSS
|
-
|
Digital GND
|
2
|
MDQ9
|
I/O
|
SRAM data bass 9
|
3
|
MDQ5
|
I/O
|
SRAM data bass 5
|
4
|
MDQ10
|
I/O
|
SRAM data bass 10
|
5
|
VDD
|
-
|
Digital power supply (3.3V)
|
6
|
MDQ4
|
I/O
|
SRAM data bass 4
|
7
|
MDQ11
|
I/O
|
SRAM data bass 11
|
8
|
MDQ3
|
I/O
|
SRAM data bass 3
|
9
|
MDQ12
|
I/O
|
SRAM data bass 12
|
10
|
VSS
|
-
|
Digital GND
|
11
|
MDQ2
|
I/O
|
SRAM data bass 2
|
12
|
LVDD
|
-
|
Internal digital logic power supply (1.5V)
|
13
|
MDQ13
|
I/O
|
SRAM data bass 13
|
14
|
MDQ1
|
I/O
|
SRAM data bass 1
|
15
|
VDD
|
-
|
Digital power supply (3.3V)
|
16
|
MDQ14
|
I/O
|
SRAM data bass 14
|
17
|
MDQ0
|
I/O
|
SRAM data bass 0
|
18
|
MDQ15
|
I/O
|
SRAM data bass 15
|
19
|
VSS
|
-
|
Digital GND
|
20
|
HMD
|
I
|
HCLK polarity selection signal
|
21
|
XRST
|
I
|
System reset terminal
|
22
|
XHINT
|
O
|
Interruption input to host (low active)
|
23
|
XHINT2
|
O
|
Interruption input to host (low active)
|
24
|
XDK
|
O
|
Data acknowledge output to host
|
25
|
XWRH
|
I
|
Write enable from host (low active)
|
26
|
VDD
|
-
|
Digital power supply (3.3V)
|
27
|
XWR
|
I
|
Write enable from host (low active)
|
28
|
XRD
|
I
|
Read enable from host (low active)
|
29
|
XCS
|
I
|
Chip select from host (low active)
|
30
|
LVDD
|
-
|
Internal digital logic power supply (1.5V)
|
31
|
HCLK
|
I
|
CLK input from host
|
32
|
HA1
|
I
|
Address input 1 from host
|
33
|
HA2
|
I
|
Address input 2 from host
|
34
|
VSS
|
-
|
Digital GND
|
35
|
HA3
|
I
|
Address input 3 from host
|
36
|
HA4
|
I
|
Address input 4 from host
|
37
|
HA5
|
I
|
Address input 5 from host
|
38
|
HA6
|
I
|
Address input 6 from host
|
39
|
VDD
|
-
|
Digital power supply (3.3V)
|
40
|
HA7
|
I
|
Address input 7 from host
|
41
|
HA8
|
I
|
Address input 8 from host
|
42
|
HA9
|
I
|
Address input 9 from host
|
43
|
HA10
|
I
|
Address input 10 from host
|
44
|
VSS
|
-
|
Digital GND
|
45
|
HA11
|
I
|
Address input 11 from host
|
46
|
HA12
|
I
|
Address input 12 from host
|
47
|
HA13
|
-
|
Address input 13 from host
|
48
|
LVDD
|
-
|
Internal digital logic power supply (1.5V)
|
49
|
HA14
|
I
|
Address input 14 from host
|
50
|
HA15
|
I
|
Address input 15 from host
|
51
|
HA16
|
I
|
Address input 16 from host
|
52
|
VDD
|
-
|
Digital power supply (3.3V)
|
53
|
VSS
|
-
|
Digital GND
|
54
|
HA17
|
I
|
Address input 17 from host
|
55
|
HD0
|
I/O
|
host data bass 0
|
56
|
HD1
|
I/O
|
Data input 1 from host
|
57
|
HD2
|
I/O
|
Data input 2 from host
|
58
|
VDD
|
-
|
Digital power supply (3.3V)
|
59
|
HD3
|
I/O
|
Data input 3 from host
|
60
|
HD4
|
I/O
|
Data input 4 from host
|
61
|
HD5
|
I/O
|
Data input 5 from host
|
62
|
VSS
|
-
|
Digital GND
|
63
|
HD6
|
I/O
|
Data input 6 from host
|
64
|
HD7
|
I/O
|
Data input 7 from host
|
65
|
HD8
|
I/O
|
Data input 8 from host
|
66
|
VDD
|
-
|
Digital power supply (3.3V)
|
67
|
HD9
|
I/O
|
Data input 9 from host
|
68
|
HD10
|
I/O
|
Data input 10 from host
|
69
|
LVDD
|
-
|
Internal digital logic power supply (1.5V)
|
70
|
HD11
|
I/O
|
Data input 11 from host
|
71
|
VSS
|
-
|
Digital GND
|
72
|
HD12
|
I/O
|
Data input 12 from host
|
73
|
HD13
|
I/O
|
Data input 13 from host
|
74
|
HD14
|
I/O
|
Data input 14 from host
|
75
|
VDD
|
-
|
Digital power supply (3.3V)
|
76
|
HD15
|
I/O
|
Data input 15 from host
|
77
|
DVALID
|
I
|
Valid signal of bit stream input data
|
78
|
DSTR
|
I
|
CLK signal for bit stream
|
79
|
STRQ
|
O
|
Request of program stream
|
80
|
VSS
|
-
|
Digital GND
|
81
|
STD7
|
I
|
Bit stream parallel input7
|
82
|
STD6
|
I
|
Bit stream parallel input6
|
83
|
STD5
|
I
|
Bit stream parallel input5
|
84
|
STD4
|
I
|
Bit stream parallel input4
|
85
|
STD3
|
I
|
Bit stream parallel input3
|
86
|
STD2
|
I
|
Bit stream parallel input2
|
87
|
STD1
|
I
|
Bit stream parallel input1
|
88
|
STD0
|
I
|
Bit stream parallel input0
|
89
|
VDD
|
-
|
Digital power supply (3.3V)
|
90
|
IECOUT
|
O
|
IEC958 format data output
|
91
|
ADOUT0
|
O
|
Audio data output (CH1/CH2)
|
92
|
ADOUT1
|
O
|
Audio data output (CH3/CH4)
|
93
|
ADOUT2
|
O
|
Audio data output (CH5/CH6)
|
94
|
ADOUT3
|
O
|
Audio data output (CH7/CH8)
|
95
|
VSS
|
-
|
Digital GND
|
96
|
SRCK
|
O
|
bit clock output
|
97
|
LRCK
|
O
|
LR clock output
|
98
|
LVDD
|
-
|
Internal digital logic power supply (1.5V)
|
99
|
PHCOPMO
|
O
|
Audio-PLL phase comparison output
|
100
|
EXTCK
|
I
|
Audio CLK input
|
101
|
CLK121
|
I
|
CLK test input terminal (L or H fix)
|
102
|
PCLK
|
I
|
Main-PLL system clock input (27MHz or 54MHz)
|
103
|
VDD
|
-
|
Digital power supply (3.3V)
|
104
|
VSS
|
-
|
Digital GND
|
105
|
PLLAVDD
|
-
|
Main-PLL power supply
|
106
|
TCPOUT
|
O
|
Main-PLL test output terminal (Used as open.)
|
107
|
PLLAVSS
|
-
|
Main-PLL GND
|
108
|
DAC3OUT
|
O
|
DAC output 3
|
109
|
DAC1OUT
|
O
|
DAC output 1
|
110
|
COMP2
|
I
|
DAC stabilization volume connection terminal 2
|
111
|
IREF2
|
I
|
Resistance terminal 2 for DAC bias current electricity setting
|
112
|
AVDD
|
-
|
DAC analog power supply (3.3V)
|
113
|
AVSS
|
-
|
DAC analog GND
|
114
|
DAC2OUT
|
O
|
DAC output 2
|
115
|
VREF
|
I
|
DAC gain adjustment terminal
|
116
|
DAC4OUT
|
O
|
DAC output 4
|
117
|
COMP1
|
I
|
DAC stabilization volume connection terminal 1
|
118
|
AVDD
|
-
|
DAC analog power supply (3.3V)
|
119
|
IREF1
|
I
|
Resistance terminal 1 for DAC bias current electricity setting
|
120
|
DAC5OUT
|
O
|
DAC output 5
|
121
|
AVSS
|
-
|
DAC analog GND
|
122
|
VSS
|
-
|
Digital GND
|
123
|
DCTEST
|
I
|
DC test mode terminal (Used as open)
|
124
|
TESTSEL2
|
I
|
Test mode terminal 2 (L fix)
|
125
|
TESTSEL1
|
I
|
Test mode terminal 1 (L fix)
|
126
|
TESTSEL0
|
I
|
Test mode terminal 0 (DAC CLK selection signal)
|
127
|
LVDD
|
-
|
Internal digital logic power supply (1.5V)
|
128
|
VCLK
|
I
|
Digital video data CLK (27MHz)
|
129
|
VDIN7
|
I
|
Digital video data input 7
|
130
|
VDIN6
|
I
|
Digital video data input 6
|
131
|
VDD
|
-
|
Digital power supply (3.3V)
|
132
|
VDIN5
|
I
|
Digital video data input 5
|
133
|
VDIN4
|
I
|
Digital video data input 4
|
134
|
VDIN3
|
I
|
Digital video data input 3
|
135
|
LVDD
|
-
|
Internal digital logic power supply (1.5V)
|
136
|
VDIN2
|
I
|
Digital video data input 2
|
137
|
VDIN1
|
I
|
Digital video data input 1
|
138
|
VDIN0
|
I
|
Digital video data input 0
|
139
|
VSS
|
-
|
Digital GND
|
140
|
VDOUT0
|
O
|
Digital video data output 0
|
141
|
VDOUT1
|
O
|
Digital video data output 1
|
142
|
VDOUT2
|
O
|
Digital video data output 2
|
143
|
VDOUT3
|
O
|
Digital video data output 3
|
144
|
VDD
|
-
|
Digital power supply (3.3V)
|
145
|
VDOUT4
|
O
|
Digital video data output 4
|
146
|
VDOUT5
|
O
|
Digital video data output 5
|
147
|
VDOUT6
|
O
|
Digital video data output 6
|
148
|
VSS
|
-
|
Digital GND
|
149
|
VDOUT7
|
O
|
Digital video data output 7
|
150
|
MDQ24
|
I/O
|
SDRAM data bass 24
|
151
|
MDQ23
|
I/O
|
SSDRAM data bass 23
|
152
|
VDD
|
-
|
Digital power supply (3.3V)
|
153
|
MDQ25
|
I/O
|
SDRAM data bass 25
|
154
|
MDQ22
|
I/O
|
SDRAM data bass 22
|
155
|
MDQ26
|
I/O
|
SDRAM data bass 26
|
156
|
VSS
|
-
|
Digital GND
|
157
|
VDD
|
-
|
Digital power supply (3.3V)
|
158
|
MDQ21
|
I/O
|
SDRAM data bass 21
|
159
|
MDQ27
|
I/O
|
SDRAM data bass 27
|
160
|
MDQ20
|
I/O
|
SDRAM data bass 20
|
161
|
VSS
|
-
|
Digital GND
|
162
|
MDQ28
|
I/O
|
SDRAM data bass 28
|
163
|
MDQ19
|
I/O
|
SDRAM data bass 19
|
164
|
MDQ29
|
I/O
|
SDRAM data bass 29
|
165
|
VDD
|
-
|
Digital power supply (3.3V)
|
166
|
MDQ18
|
I/O
|
SDRAM data bass 18
|
167
|
MDQ30
|
I/O
|
SDRAM data bass 30
|
168
|
MDQ17
|
I/O
|
SDRAM data bass 17
|
169
|
MDQ31
|
I/O
|
SDRAM data bass 31
|
170
|
VSS
|
-
|
Digital GND
|
171
|
MDQ16
|
I/O
|
SDRAM data bass 16
|
172
|
LVDD
|
-
|
Internal digital logic power supply (1.5V)
|
173
|
DQM3
|
-
|
SRAM data byte (mask signal 3)
|
174
|
DQM2
|
-
|
SRAM data byte (mask signal 2)
|
175
|
VDD
|
-
|
Digital power supply (3.3V)
|
176
|
MA3
|
O
|
SDRAM address 3
|
177
|
MA4
|
O
|
SDRAM address 4
|
178
|
MA2
|
O
|
SDRAM address 2
|
179
|
MA5
|
O
|
SDRAM address 5
|
180
|
VSS
|
-
|
Digital GND
|
181
|
MA1
|
O
|
SDRAM address 1
|
182
|
MA6
|
O
|
SDRAM address 6
|
183
|
MA0
|
O
|
SDRAM address 0
|
184
|
VDD
|
-
|
Digital power supply (3.3V)
|
185
|
MCKI
|
I
|
CLK input terminal from data input from SRAM
|
186
|
LVDD
|
-
|
Internal digital logic power supply (1.5V)
|
187
|
MCK
|
O
|
CLK output to SRAM
|
188
|
MA7
|
O
|
SDRAM address 7
|
189
|
MA10
|
O
|
SDRAM address 10
|
190
|
VSS
|
-
|
Digital GND
|
191
|
MA8
|
O
|
SDRAM address 8
|
192
|
MA11
|
O
|
SDRAM address 11
|
193
|
XWE
|
O
|
SRAM write enable signal
|
194
|
VDD
|
-
|
Digital power supply (3.3V)
|
195
|
BA0
|
-
|
SDRAM bank 0
|
196
|
MA9
|
O
|
SDRAM address 9
|
197
|
BA1
|
-
|
SDRAM bank 1
|
198
|
XCSM
|
O
|
Chip select signal for main SDRAM
|
199
|
VSS
|
-
|
Digital GND
|
200
|
XRAS
|
O
|
RAS signal for SRAM
|
201
|
XCAS
|
O
|
CAS signal for SRAM
|
202
|
DQM0
|
-
|
Data byte for SRAM (mask signal 0)
|
203
|
VDD
|
-
|
Digital power supply (3.3V)
|
204
|
DQM1
|
-
|
Data byte for SRAM (mask signal 1)
|
205
|
MDQ7
|
I/O
|
SRAM data bank 7
|
206
|
MDQ8
|
I/O
|
SRAM data bank 8
|
207
|
MDQ6
|
I/O
|
SRAM data bank 6
|
208
|
VSS
|
-
|
Digital GND
|