;************************************************************************ list p=18f4523 ; list directive to define processor radix dec errorlevel 0,-302 errorlevel 0,-306 #include ; processor specific variable definitions #include ;tamogato2 ;************************************************************************* ; ;********************************************************************** ;* CONFIGURATION REGISTER * * ;********************************************************************** ; ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 CONFIG OSC = INTIO67 ;Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: CONFIG PWRT = ON ; PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software CONFIG BOREN = OFF ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: CONFIG WDT = OFF ;WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 CONFIG WDTPS = 4096 ;1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; CCP2 MUX bit: ; CCP2MX = PORTB CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; Low-Power Timer1 Oscillator Enable bit: CONFIG LPT1OSC = OFF ; Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled CONFIG MCLRE = ON ;MCLR pin enabled; RE3 input pin disabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; CONFIG STVREN = ON ;Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: CONFIG LVP = OFF ; Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ;CONFIG DEBUG = ON ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP0 = ON Block 0 (000800-001FFFh) code-protected CONFIG CP0 = OFF ; Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit: ; CP1 = ON Block 1 (002000-003FFFh) code-protected CONFIG CP1 = OFF ;Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit: ; CP2 = ON Block 2 (004000-005FFFh) code-protected CONFIG CP2 = OFF ;Block 2 (004000-005FFFh) not code-protected ; ; Code Protection bit: ; CP3 = ON Block 3 (006000-007FFFh) code-protected CONFIG CP3 = OFF ;Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection bit: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; RÉGI ; CONFIG OSC=INTIO67 ;CONFIG FCMEN=OFF ;CONFIG IESO=OFF ;CONFIG WDT=OFF ;CONFIG PWRT=OFF ;CONFIG BOREN=OFF ;CONFIG MCLRE=ON ;CONFIG STVREN=ON ;CONFIG LVP=OFF ;CONFIG DEBUG=ON;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ;CONFIG PBADEN = OFF ;CONFIG CP0=Off ; CONFIG CP1=Off ; CONFIG CPB=Off ; CONFIG CPD=Off ; CONFIG WRT0=Off ; CONFIG WRT1=Off ; CONFIG WRTB=Off ; CONFIG WRTC=Off ; CONFIG EBTR0=Off ; CONFIG EBTR1=Off ; CONFIG EBTRB=Off ; ;**************************************************************************************************** ; ;**************************************************************************************************** ; ; ;**************************************************************** ;* D E F I N E * ;**************************************************************** ; #define led PORTB,4 #define DB4 PORTD,0 #define DB5 PORTD,1 #define DB6 PORTD,2 #define DB7 PORTD,3 #define lcd_rs PORTE,0 #define lcd_rw PORTE,1 #define lcd_e PORTE,2 #define lcd PORTD ;***** SPECIAL FILE REGISTERS ******* ; CBLOCK 0x000 del1 del2 del3 ENDC org 0 bra pos ;power on ; ;************************************************ ;* I N T E R U P T * ;************************************************ ;************************************************ ; M A I N - P R O G R A M * ;************************************************ ; pos call inic ;************ LCD INIC ********************** call del20ms call del20ms call del20ms call del20ms call del20ms movlw b'00000011' ;8bit mode x1 movwf PORTD bsf lcd_e bsf lcd_e nop nop nop nop bcf lcd_e bcf lcd_e call del20ms movlw b'00000011' ;8bit mode x2 movwf PORTD bsf lcd_e bsf lcd_e nop nop nop nop bcf lcd_e bcf lcd_e call del20ms movlw b'00000011' ;8bit mode x3 movwf PORTD bsf lcd_e bsf lcd_e nop nop nop nop bcf lcd_e bcf lcd_e call del20ms ;*** SIMA KIÍRÁS *** movlw b'00000010' ;4bit mode movwf PORTD bsf lcd_e bsf lcd_e nop nop nop nop bcf lcd_e bcf lcd_e call del20ms ;******************************************** movlw b'00000010' ;5x8 movwf PORTD bsf lcd_e bsf lcd_e nop nop nop nop bcf lcd_e bcf lcd_e call del20ms movlw b'00000000' movwf PORTD bsf lcd_e bsf lcd_e nop nop nop nop bcf lcd_e bcf lcd_e call del20ms ;******************************************** movlw b'00000000' ;control: display OFF, cursor OFF, blink OFF, movwf PORTD bsf lcd_e bsf lcd_e nop nop nop nop bcf lcd_e bcf lcd_e call del20ms movlw b'00001000' movwf PORTD bsf lcd_e bsf lcd_e nop nop nop nop bcf lcd_e bcf lcd_e call del20ms ;******************************************** movlw b'00000000' ; Clear display. movwf PORTD bsf lcd_e bsf lcd_e nop nop nop nop bcf lcd_e bcf lcd_e call del20ms movlw b'00000001' movwf PORTD bsf lcd_e bsf lcd_e nop nop nop nop bcf lcd_e bcf lcd_e call del20ms ;******************************************** movlw b'00000000' ; Display ON/OFF control: display ON, cursor ON, blink OFF, movwf PORTD bsf lcd_e bsf lcd_e nop nop nop nop bcf lcd_e bcf lcd_e call del20ms movlw b'00001110' movwf PORTD bsf lcd_e bsf lcd_e nop nop nop nop bcf lcd_e bcf lcd_e call del20ms ;**** MAIN LOOP *************************************************** ; villog bsf led call del1s bcf led call del1s goto villog ;************************************************************************ ;* S U B R U T I N S * ;************************************************************************ ; inic clrf PORTD clrf PORTE movlw B'11101111' ;7:1 PGD ;6:1 PGC ;5:1 PGM ;4:0 led ;3:1 ;2:1 ;1:1 ;0:1 movwf TRISB movlw B'11110000' ;7:1 ;6:1 ;5:1 ;4:1 ;3:1 lcd db7 ;2:1 lcd db6 ;1:1 lcd db5 ;0:0 lcd db4 movwf TRISD movlw B'11111000' ;7:1 ;6:1 ;5:1 ;4:1 ;3:1 ;2:1 E ;1:1 R/W_ ;0:0 RS movwf TRISE ;******** A/D ******************** clrf ADCON0 movlw B'00001111' ; ALL digital movwf ADCON1 return ;************************************************ ;* D E L A Y * ;************************************************ ; del1us nop nop nop nop nop nop return ;************************************************ ;* delay 100us (OK) * ;* 4MHz;20MHz * ;************************************************ ; *** ALAP *** del100us movlw 31 ;osc:4MHz 1us/inst ; movlw .165 ;osc:20Mhz 0,2us/inst nop nop nop movwf del1 del_2 decfsz del1,F bra del_2 return ; ; ;************************************************ ;* delay 20ms * ;************************************************ ;->del100us del20ms movlw 200 movwf del2 del_20ms dcfsnz del2,F return call del100us ;ALAP bra del_20ms ; ;************************************************ ;* delay 1ms (??) * ;************************************************ ; ; del1ms movlw 10 movwf del2 del_1ms dcfsnz del2,F return call del100us ;alap bra del_1ms ;;*********************************************** ; delay 0,1 sec * ;************************************************ ; del01s load del3,5 d01s dcfsnz del3,F return call del20ms bra d01s ; ;************************************************ ;* delay 1sec * ;************************************************ ; del1s load del3,50 del_1s dcfsnz del3,F return call del20ms bra del_1s end