// Verilog test fixture created from schematic C:\Documents and Settings\Developer\proba_\kapcsolas.sch - Wed Jun 13 23:55:19 2012

`timescale 1ns / 1ps

module kapcsolas_kapcsolas_sch_tb();

// Inputs
   reg B;
   reg A;
   reg CLK;

// Output
   wire Sum;
   wire Cout;

// Bidirs

// Instantiate the UUT
   kapcsolas UUT (
		.B(B), 
		.A(A), 
		.CLK(CLK), 
		.Sum(Sum), 
		.Cout(Cout)
   );
// Initialize Inputs
   `ifdef auto_init
       initial begin
		B = 0;
		A = 0;
		CLK= 0;
   `endif
	
	 
    always #5 CLK <= ~CLK;	
	
endmodule