<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
    <attr value="spartan3e" name="DeviceFamilyName">
        <trait delete="all:0" />
        <trait editname="all:0" />
        <trait edittrait="all:0" />
    </attr>
    <netlist>
        <signal name="XLXN_1" />
        <signal name="XLXN_2" />
        <signal name="XLXN_4" />
        <signal name="XLXN_5" />
        <signal name="XLXN_6" />
        <signal name="XLXN_7" />
        <signal name="XLXN_8" />
        <signal name="B" />
        <signal name="A" />
        <signal name="CLK" />
        <signal name="Sum" />
        <signal name="Cout" />
        <port polarity="Input" name="B" />
        <port polarity="Input" name="A" />
        <port polarity="Input" name="CLK" />
        <port polarity="Output" name="Sum" />
        <port polarity="Output" name="Cout" />
        <blockdef name="verilog_module">
            <timestamp>2012-6-13T20:29:36</timestamp>
            <rect width="256" x="64" y="-128" height="128" />
            <line x2="0" y1="-96" y2="-96" x1="64" />
            <line x2="0" y1="-32" y2="-32" x1="64" />
            <line x2="384" y1="-96" y2="-96" x1="320" />
        </blockdef>
        <blockdef name="xor2">
            <timestamp>2000-1-1T10:10:10</timestamp>
            <line x2="64" y1="-64" y2="-64" x1="0" />
            <line x2="60" y1="-128" y2="-128" x1="0" />
            <line x2="208" y1="-96" y2="-96" x1="256" />
            <arc ex="44" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
            <arc ex="64" ey="-144" sx="64" sy="-48" r="56" cx="32" cy="-96" />
            <line x2="64" y1="-144" y2="-144" x1="128" />
            <line x2="64" y1="-48" y2="-48" x1="128" />
            <arc ex="128" ey="-144" sx="208" sy="-96" r="88" cx="132" cy="-56" />
            <arc ex="208" ey="-96" sx="128" sy="-48" r="88" cx="132" cy="-136" />
        </blockdef>
        <block symbolname="verilog_module" name="XLXI_1">
            <blockpin signalname="XLXN_4" name="A" />
            <blockpin signalname="CLK" name="B" />
            <blockpin signalname="XLXN_1" name="Y" />
        </block>
        <block symbolname="verilog_module" name="XLXI_2">
            <blockpin signalname="A" name="A" />
            <blockpin signalname="CLK" name="B" />
            <blockpin signalname="XLXN_2" name="Y" />
        </block>
        <block symbolname="verilog_module" name="XLXI_3">
            <blockpin signalname="XLXN_1" name="A" />
            <blockpin signalname="XLXN_2" name="B" />
            <blockpin signalname="Cout" name="Y" />
        </block>
        <block symbolname="xor2" name="XLXI_5">
            <blockpin signalname="CLK" name="I0" />
            <blockpin signalname="XLXN_4" name="I1" />
            <blockpin signalname="Sum" name="O" />
        </block>
        <block symbolname="xor2" name="XLXI_6">
            <blockpin signalname="B" name="I0" />
            <blockpin signalname="A" name="I1" />
            <blockpin signalname="XLXN_4" name="O" />
        </block>
    </netlist>
    <sheet sheetnum="1" width="3520" height="2720">
        <instance x="1536" y="1184" name="XLXI_1" orien="R0">
        </instance>
        <instance x="1600" y="1616" name="XLXI_2" orien="R0">
        </instance>
        <instance x="2320" y="1376" name="XLXI_3" orien="R0">
        </instance>
        <branch name="XLXN_1">
            <wire x2="2112" y1="1088" y2="1088" x1="1920" />
            <wire x2="2112" y1="1088" y2="1280" x1="2112" />
            <wire x2="2320" y1="1280" y2="1280" x1="2112" />
        </branch>
        <branch name="XLXN_2">
            <wire x2="2144" y1="1520" y2="1520" x1="1984" />
            <wire x2="2320" y1="1344" y2="1344" x1="2144" />
            <wire x2="2144" y1="1344" y2="1520" x1="2144" />
        </branch>
        <instance x="816" y="560" name="XLXI_6" orien="R0" />
        <instance x="1280" y="800" name="XLXI_5" orien="R0" />
        <branch name="XLXN_4">
            <wire x2="1168" y1="464" y2="464" x1="1072" />
            <wire x2="1168" y1="464" y2="672" x1="1168" />
            <wire x2="1280" y1="672" y2="672" x1="1168" />
            <wire x2="1168" y1="672" y2="1088" x1="1168" />
            <wire x2="1536" y1="1088" y2="1088" x1="1168" />
        </branch>
        <branch name="B">
            <wire x2="816" y1="496" y2="496" x1="592" />
        </branch>
        <branch name="A">
            <wire x2="720" y1="432" y2="432" x1="592" />
            <wire x2="816" y1="432" y2="432" x1="720" />
            <wire x2="720" y1="432" y2="1520" x1="720" />
            <wire x2="1600" y1="1520" y2="1520" x1="720" />
        </branch>
        <branch name="CLK">
            <wire x2="656" y1="736" y2="736" x1="592" />
            <wire x2="960" y1="736" y2="736" x1="656" />
            <wire x2="1280" y1="736" y2="736" x1="960" />
            <wire x2="960" y1="736" y2="1152" x1="960" />
            <wire x2="1536" y1="1152" y2="1152" x1="960" />
            <wire x2="656" y1="736" y2="1584" x1="656" />
            <wire x2="1600" y1="1584" y2="1584" x1="656" />
        </branch>
        <branch name="Sum">
            <wire x2="2768" y1="704" y2="704" x1="1536" />
            <wire x2="2912" y1="704" y2="704" x1="2768" />
        </branch>
        <branch name="Cout">
            <wire x2="2864" y1="1280" y2="1280" x1="2704" />
        </branch>
        <iomarker fontsize="28" x="592" y="432" name="A" orien="R180" />
        <iomarker fontsize="28" x="592" y="496" name="B" orien="R180" />
        <iomarker fontsize="28" x="592" y="736" name="CLK" orien="R180" />
        <iomarker fontsize="28" x="2912" y="704" name="Sum" orien="R0" />
        <iomarker fontsize="28" x="2864" y="1280" name="Cout" orien="R0" />
    </sheet>
</drawing>