// Verilog test fixture created from schematic C:\Documents and Settings\Pinyo\Xilinx\Own Projects\HE_help\kapcsolas.sch - Mon Jun 18 22:10:54 2012

`timescale 1ns / 1ps

module kapcsolas_kapcsolas_sch_tb();

// Inputs
   reg B;
   reg A;
   reg CLK;

// Output
   wire Sum;
   wire Cout;

// Bidirs

// Instantiate the UUT
   kapcsolas UUT (
		.B(B), 
		.A(A), 
		.Sum(Sum), 
		.Cout(Cout), 
		.CLK(CLK)
   );
// Initialize Inputs
	initial 
		begin
			B = 0;
			A = 0;
			CLK = 0;
		end
 
	always #5 CLK <= ~CLK;
	
	reg [1:0] cnt = 2'b0;
	always@(posedge CLK)
	begin
		cnt <= cnt + 1'b1;
		A <= cnt[0];
		B <= cnt[1];
	end
	
endmodule