.SUBCKT szamolo IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 GND VCCVCC VCC 0 dc 5 aU3 [dU3.notLT + dU3.notRBI + 4 + 3 + 2 + 1 + dU3.notBIbackslashRBO + rU3.OA + rU3.OB + rU3.OC + rU3.OD + rU3.OE + rU3.OF + rU3.OG] + [dU3.OA + dU3.OB + dU3.OC + dU3.OD + dU3.OE + dU3.OF + dU3.OG] 74LS47__74STD__1 xU3.OA ~dU3.OA IO1 VCC GND TTL_DRVOC__NON__1 xU3.OD ~dU3.OD IO4 VCC GND TTL_DRVOC__NON__1 xU3.OE ~dU3.OE IO5 VCC GND TTL_DRVOC__NON__1 xU3.OF ~dU3.OF IO6 VCC GND TTL_DRVOC__NON__1 xU3.OC ~dU3.OC IO3 VCC GND TTL_DRVOC__NON__1 xU3.OB ~dU3.OB IO2 VCC GND TTL_DRVOC__NON__1 xU3.OG ~dU3.OG IO7 VCC GND TTL_DRVOC__NON__1 xU3.notLT VCC dU3.notLT VCC GND TTL_RCV__NON__1 xU3.notRBI VCC dU3.notRBI VCC GND TTL_RCV__NON__1 xU3.notBIbackslashRBO VCC dU3.notBIbackslashRBO VCC GND TTL_RCV__NON__1 aU2 [dU2.INA + 1 + dU2.R01 + dU2.R02 + dU2.R91 + dU2.R92] + [1 + 2 + 3 + 4] 7490__74STD__1 xU2.R91 GND dU2.R91 VCC GND TTL_RCV__NON__1 xU2.R92 GND dU2.R92 VCC GND TTL_RCV__NON__1 xU2.R01 GND dU2.R01 VCC GND TTL_RCV__NON__1 xU2.INA IO8 dU2.INA VCC GND TTL_RCV__NON__1 xU2.R02 GND dU2.R02 VCC GND TTL_RCV__NON__1 .SUBCKT TTL_DRVOC__NON__1 1 2 3 4 aDACin1 [1] [8] aDAC R1 5 3 1.6K R2 4 6 1K Q1 5 8 6 Qideal Q2 2 6 4 Qideal * .MODEL Qideal NPN (rb= 10 is= 1e-14 bf= 400 re= 10 rc= 10 cje=2p cjc=2p) .MODEL aDAC dac_bridge (out_low= 0.8 out_high = 2.0 out_undef= 0.8 ) .ENDS .MODEL 74LS47__74STD__1 d_chip ( behaviour= " +;74LS47 BCD TO SEVEN-SEGMENT DISPLAY OC 15V OUTPUTS +/inputs ~LT ~RBI D C B A ~BI/RBO +/outputs OA OB OC OD OE OF OG +/table 20 +; LT' RBI' D C B A BI/RBO' A B C D E F G + H H L L L L H L L L L L L H + H H L L L H H H L L H H H H + H H L L H L H L L H L L H L + H H L L H H H L L L L H H L + H H L H L L H H L L H H L L + H H L H L H H L H L L H L L + H H L H H L H H H L L L L L + H H L H H H H L L L H H H H + H H H L L L H L L L L L L L + H H H L L H H L L L H H L L + H H H L H L H H H H L L H L + H H H L H H H H H L L H H L + H H H H L L H H L H H H L L + H H H H L H H L H H L H L L + H H H H H L H H H H L L L L + H H H H H H H H H H H H H H + X X X X X X L H H H H H H H + H L L L L L L H H H H H H H + L X X X X X H L L L L L L L + H X X X X X H L L L L L L L +/delay 42 +;input output rise time fall time + A OA 100n 100n + A OB 100n 100n + A OC 100n 100n + A OD 100n 100n + A OE 100n 100n + A OF 100n 100n + A OG 100n 100n + B OA 100n 100n + B OB 100n 100n + B OC 100n 100n + B OD 100n 100n + B OE 100n 100n + B OF 100n 100n + B OG 100n 100n + C OA 100n 100n + C OB 100n 100n + C OC 100n 100n + C OD 100n 100n + C OE 100n 100n + C OF 100n 100n + C OG 100n 100n + D OA 100n 100n + D OB 100n 100n + D OC 100n 100n + D OD 100n 100n + D OE 100n 100n + D OF 100n 100n + D OG 100n 100n + ~RBI OA 100n 100n + ~RBI OB 100n 100n + ~RBI OC 100n 100n + ~RBI OD 100n 100n + ~RBI OE 100n 100n + ~RBI OF 100n 100n + ~RBI OG 100n 100n + ~LT OA 100n 100n + ~LT OB 100n 100n + ~LT OC 100n 100n + ~LT OD 100n 100n + ~LT OE 100n 100n + ~LT OF 100n 100n + ~LT OG 100n 100n +") .SUBCKT TTL_RCV__NON__1 1 2 3 4 * TTL LOAD Model 1 = input, 2 = A/D out 3 = VCC 4= GND *#L1 aADC1in [1] [2] ADC1 .MODEL ADC1 adc_bridge (in_low= 2.5 in_high = 2.5 ) *#L1 .ENDS .MODEL 7490__74STD__1 d_chip ( behaviour= " +; 7490 DECADE COUNTER +/inputs INA INB R01 R02 R91 R92 +/outputs QA QB QC QD +/module CNT_90A +/inputs IN R01 R02 R91 R92 +/outputs Q +;clock input_number edge{+|-} number_of_flags sync_entries async_entries +/clock IN - 1 1 3 +;SYNC +; IN R01 R02 R91 R92 F NF + X X X X X X F+0 +;ASYNC +; IN R01 R02 R91 R92 F NF + X H H X X X L + X X X H H X H + X X X X X X F0 +/table 1 +; IN R01 R02 R91 R92 F Q + X X X X X X F0 +/delay 5 +;input output Rise time Fall time + IN Q 16n 18n + R01 Q X 40n + R02 Q X 40n + R91 Q X 30n + R92 Q X 30n +/constraint 9 +; Name Event From Event To Min/Max Time + 'PULSE WIDTH' LH IN HL IN MIN 15n + 'PULSE WIDTH' LH R01 HL R01 MIN 15n + 'PULSE WIDTH' LH R02 HL R02 MIN 15n + 'PULSE WIDTH' LH R91 HL R91 MIN 15n + 'PULSE WIDTH' LH R92 HL R92 MIN 15n + 'SETUP' HL IN HL R01 MIN 30n + 'SETUP' HL IN HL R02 MIN 30n + 'SETUP' HL IN HL R91 MIN 30n + 'SETUP' HL IN HL R92 MIN 30n +/endmodule +/module CNT_90B +/inputs IN R01 R02 R91 R92 +/outputs Q1 Q2 Q3 +/clock IN - 3 6 3 +;SYNC +; IN R01 R02 R91 R92 F F F NF NF NF + X X X X X L L H L L L + X X L X L X X X F+0 F+1 F+2 + X L X L X X X X F+0 F+1 F+2 + X L X L X X X X F+0 F+1 F+2 + X X L L X X X X F+0 F+1 F+2 + X X X X X X X X F0 F1 F2 +;ASYNC +; IN R01 R02 R91 R92 F F F NF NF NF + X H H X X X X X L L L + X X X H H X X X L L H + X X X X X X X X F0 F1 F2 +/table 1 +; IN R01 R02 R91 R92 F F F Q1 Q2 Q3 + X X X X X X X X F0 F1 F2 +/delay 15 +;input output Rise time Fall time + IN Q1 16n 21n + IN Q2 32n 35n + IN Q3 32n 35n + R01 Q1 X 40n + R02 Q1 X 40n + R01 Q2 X 40n + R02 Q2 X 40n + R01 Q3 X 40n + R02 Q3 X 40n + R91 Q1 X 40n + R92 Q1 X 40n + R91 Q2 X 40n + R92 Q2 X 40n + R91 Q3 X 30n + R92 Q3 X 30n +/constraint 9 +; Name Event From Event To Min/Max Time + 'PULSE WIDTH' LH IN HL IN MIN 30n + 'PULSE WIDTH' LH R01 HL R01 MIN 15n + 'PULSE WIDTH' LH R02 HL R02 MIN 15n + 'PULSE WIDTH' LH R91 HL R91 MIN 15n + 'PULSE WIDTH' LH R92 HL R92 MIN 15n + 'SETUP' HL IN HL R01 MIN 30n + 'SETUP' HL IN HL R02 MIN 30n + 'SETUP' HL IN HL R91 MIN 30n + 'SETUP' HL IN HL R92 MIN 30n +/endmodule +/instance CNT_90A INA R01 R02 R91 R92 QA +/instance CNT_90B INB R01 R02 R91 R92 QB QC QD +") .ENDS