#include <ssd1963.h>
//-------------------------------------------------------------------------------------------------------------------------
void	DMA2_Stream0_IRQHandler	(void)	__irq
	{		DMA2->LIFCR = 0x30;											//Clear DMA2Stream0 Interrupt							
			DMA2_Stream0->NDTR			= 64000;				//DMA transfer consist of 64000 element (additional)
		//itt switch case szerkezettel meg lehet írni az adott kiküldést.
		
			DMA2_Stream0->CR			|= 0x01;			//Enable DMA2Stream0, next part of the TFT can be processed			
			}	
//-------------------------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------------------------
void	Delay (void)
	{		f=0;
			while	(f !=64)
			{f++;
			}
		}

//-------------------------------------------------------------------------------------------------------------------------
void	SSDComplette (void)
	{
//-------------------------------------------------------------------------------------------------------------------------
			//Init GPIO's for SSD1963. The pins for SRAM is allready preconfigured in the system_stm32f2xx.c, but only the GPIOs
			//FSMC style
			//TFT on Bank 1, Region 4
			//Connected as follow:
			//	TFT		FSMC		GPIO		NrProc		NrCon
			//---------------------------------------
			//	RS		A0			PF0			10				39		
			//	#CS		NE4			PG12		127				17
			//	#RD		NOE			PD4			118				10
			//	#WR		NWE			PD5			119				11
			//	#RST	---			PB15		76				90
			//---------------------------------------
			//	D15		D15			PD10		79				85
			//	D14		D14			PD9			78				88
			//	D13		D13			PD8			77				87
			//	D12		D12			PE15		68				96
			//	D11		D11			PE14		67				95
			//	D10		D10			PE13		66				98
			//	D9		D9			PE12		65				97
			//	D8		D8			PE11		64				100
			//	D7		D7			PE10		63				99
			//	D6		D6			PE9			60				102
			//	D5		D5			PE8			59				101
			//	D4		D4			PE7			58				104
			//	D3		D3			PD1			115				7
			//	D2		D2			PD0			114				6
			//	D1		D1			PD15		86				82
			//	D0		D0			PD14		85				81
			//Complette Memory Area	:	

				//Enabling the GPIOs, and the FSMC	
					RCC->AHB1ENR 			|= 0x7A;																		//Enable			Port B, D, E, F, G
					RCC->AHB3ENR			= 0x01;																			//Enable FSMC

				//Configure the PINs, to Output, 100MHz, and AF12
				//B
					GPIOB->MODER			|= 0x40000000;															//Output: 		PB[15]			Reset
					GPIOB->OSPEEDR		|= 0xC0000000;	
				//D
					GPIOD->MODER			|= 0xA02A0A0A;															//Output: 		PD[15,14,10,9,8,5,4,1,0]
					GPIOD->OSPEEDR		|= 0xF03F0F0F;															//HighSpeed:	
					GPIOD->AFR[1]			|= 0xCC000CCC;															//Switch to: AF12 (FSMC)	H
					GPIOD->AFR[0]			|= 0x00CC00CC;															//												L
				//E
					GPIOE->MODER			|= 0xAAAA8000;															//Output:			PE[15,14,13,12,11,10,9,8,7]
					GPIOE->OSPEEDR		|= 0xFFFFC000;															//High Speed:
					GPIOE->AFR[1]			|= 0xCCCCCCCC;															//Switch to:	AF12 (FSMC)	H
					GPIOE->AFR[0]			|= 0xC0000000;															//												L
				//F
					GPIOF->MODER			|= 0x02;																		//Output:			PF[0]
					GPIOF->OSPEEDR		|= 0x03;																		//High Speed:
					GPIOF->AFR[0]			|= 0x0C;																		//Switch to:	AF12 (FSMC)	L
			//G
					GPIOG->MODER			|= 0x02000000;															//Output:			PG[12]
					GPIOG->OSPEEDR		|= 0x03000000;															//High Speed:							
					GPIOG->AFR[1]			|= 0x000C0000;															//Switch to:	AF12 (FSMC)	H
//-------------------------------------------------------------------------------------------------------------------------
//FSMC configuration for the SSD1963 on the FSMC-NE4 /Bank1-4/
					FSMC_Bank1->BTCR[6]		=		0x00001058;													//BCR4
					FSMC_Bank1->BTCR[7]		=		0x10000200;													//BTR4
		//Enable the Bank1 Area4
					FSMC_Bank1->BTCR[6]		|=	0x01;																//BCR4
//-------------------------------------------------------------------------------------------------------------------------
//Onboard 512k SRAM configuration
		//Need to configure FSMC_A18 additionaly: default is only configured up to A17
					GPIOD->MODER			= 0xAAAA0A0A;																//Output:			PD[13]
					GPIOD->OSPEEDR		= 0xFFFF0F0F;																//High Speed:							
					GPIOD->AFR[1]			= 0xCCCCCCCC;																//Switch to:	AF12 (FSMC)	H
	//Setup the onboard SRAM on FSMC NE2 (pins preconfigured in system_stm32f2xx.c)
					FSMC_Bank1->BTCR[3]		= 0x00000300;														//0x00010200;
					FSMC_Bank1->BTCR[2]		= 0x00001011;
//-------------------------------------------------------------------------------------------------------------------------
//Software configuration of SSD1963 with the preconfigured config-holder array
					RST_High;																											//Relase SSD1963 from reset
					Delay	();																											//Delay after the relase from reset
//Recalculate TFT Config
		//PLL
					SSDconfig[5] = (SSD_VCOFreq / SSDFxtal) - 1;
					SSDconfig[6] = (SSD_VCOFreq / SSD_PLLFreq) - 1;
		//Lshift Freq;
					i = ((1048576 * PixelFreq) / SSD_PLLFreq) - 1;
					SSDconfig[18] = i >> 16;
					SSDconfig[19] = i >>	8;
					SSDconfig[20] = i >>	0;
		
		//Horizontal Period
			//HT: Horizontal Total Period (HT) = HSYNCperiod - 1
					SSDconfig[35]	= 0x04;																					//(HSYNCperiod -1) >> 8;
					SSDconfig[36] = 0x1F;																					//(HSYNCperiod - 1);
			//HPS: Horizontal Pulse Start Position = HSYNCpulsewdth + HSYNCbackporch
					SSDconfig[37] = (HSYNCpulsewidth + HSYNCbackporch) >> 8;
					SSDconfig[38] =	(HSYNCpulsewidth + HSYNCbackporch);
			//HPW: Horizontal Sync Pulse width
					SSDconfig[39]	=	HSYNCpulsewidth;
			//LPS:	Horizontal Display Period Start Position
					SSDconfig[40]	= 0;
					SSDconfig[41]	= 0;
		
		//Vertical Period
			//VT: Vertical Total
					SSDconfig[45] = (VSYNCperiod - 1) >> 8;
					SSDconfig[46] = (VSYNCperiod - 1);
			//VPS: Vertical Sync Pulse Start Position
					SSDconfig[47] = (VSYNCpulsewidth + VSYNCbackporch) >> 8;
					SSDconfig[48] = (VSYNCpulsewidth + VSYNCbackporch);
			//VPW:	Vertical Sync Pulse Width
					SSDconfig[49] = VSYNCpulsewidth - 1;
			//FPS:	Vertical Display Period Start Position
					SSDconfig[50] =	0; 	
					SSDconfig[51] = 0;
		
		//Setup by table
		a = 1;
		do	{	LCD_REG = SSDconfig [a];																			//1st element to the Databus:						The Command
					a++;																													//Step to the next config element:			Nr of parameters
					b = SSDconfig [a];
					Delay ();
					switch	(b)
						{ case	0:	break;
							default:	do	{	a++;																			//Step to the next config element:	Data[] (0,1,2...)
																LCD_RAM = SSDconfig [a];
																b--;																		//Count down the parameter counter
																Delay ();
															}while	(b != 0);
												break;
							}
					a++;																													//Step to the next Command Line
				}while (a != SSDconfig [0]);

//-------------------------------------------------------------------------------------------------------------------------
//DMA driven version, based on the TMR interrupt witch provides the 25fps interrupt
//-------------------------------------------------------------------------------------------------------------------------
	//DMA configuration:
		//CH1(empty), mem/pher single transfer, single buffer,
		RCC->AHB1ENR				|= 0x00400000;																	//Enable DMA2 system
		DMA2_Stream0->CR		= 0x02032A90;																		//Configure the DMA	Original:0x02032A90 
		DMA2_Stream0->NDTR	= PacketNr;																			//DMA transfer consist of 64000 transfer
		DMA2_Stream0->PAR		= 0x64000000;																		//Source Address:				SRAM in FSMC Bank0, Setror 2 (NE2)
		DMA2_Stream0->M0AR	= 0x6c000002;																		//Destination Address:	TFT in FSMC Bank0, Sector 4 (NE4)
		NVIC->ISER[1]				= (1 << 24);																		//Enable DMA2Stream0 Interrupt

}