unit P16F84A;

// Individual bit access constants
const B0 = 0;
const B1 = 1;
const B2 = 2;
const B3 = 3;
const B4 = 4;
const B5 = 5;
const B6 = 6;
const B7 = 7;

const __FLASH_SIZE : dword = 0x00000400;

// Working space registers
var
  R0  : byte; rx;
  R1  : byte; rx;
  R2  : byte; rx;
  R3  : byte; rx;
  R4  : byte; rx;
  R5  : byte; rx;
  R6  : byte; rx;
  R7  : byte; rx;
  R8  : byte; rx;
  R9  : byte; rx;
  R10 : byte; rx;
  R11 : byte; rx;
  R12 : byte; rx;
  R13 : byte; rx;
  R14 : byte; rx;
  R15 : byte; rx;

const W = 0; register;
const F = 1; register;

const ICS_AUTO                  =     0;
const ICS_OFF                   =     3;


// Special function registers (SFRs)
var
  INDF             : byte; absolute 0x0000; volatile; sfr;
  TMR0             : byte; absolute 0x0001; volatile; sfr;
  PCL              : byte; absolute 0x0002; volatile; sfr;
  STATUS           : byte; absolute 0x0003; volatile; sfr;
  FSR              : byte; absolute 0x0004;           sfr;
  FSRPTR           :^byte; absolute 0x0004;           sfr;
  EEDATA           : byte; absolute 0x0008; volatile; sfr;
  EEADR            : byte; absolute 0x0009; volatile; sfr;
  PCLATH           : byte; absolute 0x000A; volatile; sfr;
  INTCON           : byte; absolute 0x000B; volatile; sfr;
  OPTION_REG       : byte; absolute 0x0081; volatile; sfr;
  EECON1           : byte; absolute 0x0088; volatile; sfr;
  EECON2           : byte; absolute 0x0089; volatile; sfr;
  PORTA            : byte; absolute 0x0005; volatile; sfr;
  PORTB            : byte; absolute 0x0006; volatile; sfr;
  TRISA            : byte; absolute 0x0085; volatile; sfr;
  TRISB            : byte; absolute 0x0086; volatile; sfr;

    // STATUS bits
    const C = 0; register;
    var   C_bit : sbit at STATUS.B0;
    const DC = 1; register;
    var   DC_bit : sbit at STATUS.B1;
    const Z = 2; register;
    var   Z_bit : sbit at STATUS.B2;
    const NOT_PD = 3; register;
    var   NOT_PD_bit : sbit at STATUS.B3;
    const NOT_TO = 4; register;
    var   NOT_TO_bit : sbit at STATUS.B4;
    const IRP = 7; register;
    var   IRP_bit : sbit at STATUS.B7;
    const RP0 = 5; register;
    var   RP0_bit : sbit at STATUS.B5;
    const RP1 = 6; register;
    var   RP1_bit : sbit at STATUS.B6;

    // INTCON bits
    const RBIF = 0; register;
    var   RBIF_bit : sbit at INTCON.B0;
    const INTF = 1; register;
    var   INTF_bit : sbit at INTCON.B1;
    const T0IF = 2; register;
    var   T0IF_bit : sbit at INTCON.B2;
    const RBIE = 3; register;
    var   RBIE_bit : sbit at INTCON.B3;
    const INTE = 4; register;
    var   INTE_bit : sbit at INTCON.B4;
    const T0IE = 5; register;
    var   T0IE_bit : sbit at INTCON.B5;
    const EEIE = 6; register;
    var   EEIE_bit : sbit at INTCON.B6;
    const GIE = 7; register;
    var   GIE_bit : sbit at INTCON.B7;
    const TMR0IF = 2; register;
    var   TMR0IF_bit : sbit at INTCON.B2;
    const TMR0IE = 5; register;
    var   TMR0IE_bit : sbit at INTCON.B5;

    // OPTION_REG bits
    const PSA = 3; register;
    var   PSA_bit : sbit at OPTION_REG.B3;
    const T0SE = 4; register;
    var   T0SE_bit : sbit at OPTION_REG.B4;
    const T0CS = 5; register;
    var   T0CS_bit : sbit at OPTION_REG.B5;
    const INTEDG = 6; register;
    var   INTEDG_bit : sbit at OPTION_REG.B6;
    const NOT_RBPU = 7; register;
    var   NOT_RBPU_bit : sbit at OPTION_REG.B7;
    const PS0 = 0; register;
    var   PS0_bit : sbit at OPTION_REG.B0;
    const PS1 = 1; register;
    var   PS1_bit : sbit at OPTION_REG.B1;
    const PS2 = 2; register;
    var   PS2_bit : sbit at OPTION_REG.B2;

    // EECON1 bits
    const RD = 0; register;
    var   RD_bit : sbit at EECON1.B0;
    const WR = 1; register;
    var   WR_bit : sbit at EECON1.B1;
    const WREN = 2; register;
    var   WREN_bit : sbit at EECON1.B2;
    const WRERR = 3; register;
    var   WRERR_bit : sbit at EECON1.B3;
    const EEIF = 4; register;
    var   EEIF_bit : sbit at EECON1.B4;

    // PORTA bits
    const RA4 = 4; register;
    var   RA4_bit : sbit at PORTA.B4;
    const RA3 = 3; register;
    var   RA3_bit : sbit at PORTA.B3;
    const RA2 = 2; register;
    var   RA2_bit : sbit at PORTA.B2;
    const RA1 = 1; register;
    var   RA1_bit : sbit at PORTA.B1;
    const RA0 = 0; register;
    var   RA0_bit : sbit at PORTA.B0;

    // PORTB bits
    const RB7 = 7; register;
    var   RB7_bit : sbit at PORTB.B7;
    const RB6 = 6; register;
    var   RB6_bit : sbit at PORTB.B6;
    const RB5 = 5; register;
    var   RB5_bit : sbit at PORTB.B5;
    const RB4 = 4; register;
    var   RB4_bit : sbit at PORTB.B4;
    const RB3 = 3; register;
    var   RB3_bit : sbit at PORTB.B3;
    const RB2 = 2; register;
    var   RB2_bit : sbit at PORTB.B2;
    const RB1 = 1; register;
    var   RB1_bit : sbit at PORTB.B1;
    const RB0 = 0; register;
    var   RB0_bit : sbit at PORTB.B0;

    // TRISA bits
    const TRISA4 = 4; register;
    var   TRISA4_bit : sbit at TRISA.B4;
    const TRISA3 = 3; register;
    var   TRISA3_bit : sbit at TRISA.B3;
    const TRISA2 = 2; register;
    var   TRISA2_bit : sbit at TRISA.B2;
    const TRISA1 = 1; register;
    var   TRISA1_bit : sbit at TRISA.B1;
    const TRISA0 = 0; register;
    var   TRISA0_bit : sbit at TRISA.B0;

    // TRISB bits
    const TRISB7 = 7; register;
    var   TRISB7_bit : sbit at TRISB.B7;
    const TRISB6 = 6; register;
    var   TRISB6_bit : sbit at TRISB.B6;
    const TRISB5 = 5; register;
    var   TRISB5_bit : sbit at TRISB.B5;
    const TRISB4 = 4; register;
    var   TRISB4_bit : sbit at TRISB.B4;
    const TRISB3 = 3; register;
    var   TRISB3_bit : sbit at TRISB.B3;
    const TRISB2 = 2; register;
    var   TRISB2_bit : sbit at TRISB.B2;
    const TRISB1 = 1; register;
    var   TRISB1_bit : sbit at TRISB.B1;
    const TRISB0 = 0; register;
    var   TRISB0_bit : sbit at TRISB.B0;
implementation
end.