; WS2812 LEDSZALAG MEGHAJTÓ ;MAX 37 LED, MERT NINCS TÖBB MEMŐRIA ;KIJELZENDŐ KÉP FSR1 = 5F NÉL KEZDŐDIK ;ZÖLD VÖRÖS KÉK SORRENDBEN ;UTOLSÓ A 01 BYTE ON ;pic16F1503 PROCESSZORRAL. ;MELLÉKESEN A KÉP TÖRLŐDIK; PROCESSOR 16F1503 INCLUDE P16F1503.INC ERRORLEVEL -302 ; disable warning (Bankswitching) ERRORLEVEL -306 ; disable warning (Pageswitching) __CONFIG _CONFIG1,_FOSC_ECH& _CLKOUTEN_OFF&_WDTE_OFF&_PWRTE_OFF&_MCLRE_ON&_CP_OFF&_BOREN_OFF &_FOSC_INTOSC __CONFIG _CONFIG2,_LVP_OFF & _STVREN_ON &_WRT_OFF CBLOCK ENDC CBLOCK 70 JB NUM ;LED SZÁMA LUME ;FÉNYERŐ ORA S_ORA MIN SEC JB2 ENDC #DEFINE ZOLD JB,1 #DEFINE KEK JB,2 #DEFINE PIROS JB,3 #DEFINE ZO 1 #DEFINE KE 2 #DEFINE PI 3 #DEFINE KIJ JB2,1 LED MACRO LED,SZIN,FENY MOVLW LED MOVWF NUM ;HELY MENTÉSE CLRF JB BSF JB,SZIN MOVLW FENY MOVWF LUME CALL LED_K ENDM ;KONSTANSOK ; AH_OSZT =4500 1 A TÖLTŐÁRAM ESETÉN 0.01 AH FELBONTÁSSAL ; =45000 0,1 A ; ; ; ORG 0 CLRF STATUS CLRF PCLATH GOTO START ORG 04 NOP BANKSEL PIR1 BCF PIR1,TMR1IF BANKSEL TMR1L MOVLW 0XDD ADDWF TMR1L MOVLW 0XF0 ADDWFC TMR1H INCF SEC MOVLW 0X3C XORWF SEC,W BTFSS STATUS,Z BRA VEG CLRF SEC INCF MIN,F MOVLW D'60' XORWF MIN,W BTFSS STATUS,Z BRA LEP CLRF MIN LEP INCF S_ORA MOVLW D'12' XORWF S_ORA,W BTFSS STATUS,Z BRA VEG CLRF S_ORA INCF ORA MOVLW D'60' XORWF ORA,W BTFSS STATUS,Z BRA VEG CLRF ORA VEG MOVLW 0X20 MOVWF FSR1H MOVFW ORA MOVWF NUM CLRF JB BSF PIROS MOVLW 0X0F MOVWF LUME CALL LED_K MOVFW MIN MOVWF NUM CLRF JB BSF ZOLD MOVLW 0X0F MOVWF LUME CALL LED_K MOVFW SEC MOVWF NUM CLRF JB BSF KEK MOVLW 0X0F MOVWF LUME CALL LED_K BSF KIJ RETFIE ;MÉRÉSEK BEFEJEZÉSE ORG 100 START ;bit 7 Unimplemented: Read as ‘0’ ;bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits ; 1111 =16MHz ; 1110 =8MHz ; 1101 =4MHz ; 1100 =2MHz ; 1011 =1MHz ; 1010 =500kHz(1) ; 1001 =250kHz(1) ; 1000 =125kHz(1) ; 0111 = 500 kHz (default upon Reset) ; 0110 =250kHz ; 0101 =125kHz ; 0100 =62.5kHz ; 001x =31.25kHz ; 000x = 31 kHz (LFINTOSC) ;bit 2 Unimplemented: Read as ‘0’ ;bit 1-0 SCS<1:0>: System Clock Select bits ; 1x = Internal oscillator block ; 01 = Reserved ; 00 = Clock determined by FOSC<1:0> in Configuration Words. BANKSEL OSCCON MOVLW B'01111010' ;OSC= 2MHZ MOVWF OSCCON MOVLW 20 ;MEMÓRIA TÖRLÉS MOVWF FSR1H MOVLW 00 MOVWF FSR1L MOVLW 00 MEM MOVWF INDF1 INCFSZ FSR1L,f BRA MEM INCF FSR1H,F BTFSS FSR1H,2 BRA MEM MOVLW 070 MOVWF FSR1L MOVLW 00 MOVWF FSR1H MOVLW 0 MEM1 MOVWF INDF1 ;JUKAK TÖRLÉSE INCF FSR1L,f BTFSS FSR1L,7 BRA MEM1 BANKSEL TRISA MOVLW B'11111111' MOVWF TRISA MOVLW B'11111010' ;SDO KIMENET MOVWF TRISC BANKSEL ANSELA MOVLW B'00000000' ;MINDEN PORT DIGITÁLIS MOVWF ANSELA MOVLW B'00000000' MOVWF ANSELC BANKSEL PIE1 BCF PIE1,SSP1IE ;MEGSZAKÍTÁS ENGEDÉLYEZÉSE BSF INTCON ,PEIE BSF INTCON ,GIE ;SPI MEGSZAKÍTÁS ENGEDÉLYEZÉSE ; sspcon ;bit 7 WCOL: Write Collision Detect bit ;Master mode: ;1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started ;0 = No collision ;Slave mode: ;1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) ;0 = No collision ;bit 6 SSPOV: Receive Overflow Indicator bit(1) ;In SPI mode: ;1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. ;Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid ;setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the ;SSPxBUF register (must be cleared in software). ;0 = No overflow ;In I2 C mode: ;1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode ;(must be cleared in software). ;0 = No overflow ;bit 5 SSPEN: Synchronous Serial Port Enable bit ;In both modes, when enabled, these pins must be properly configured as input or output ;In SPI mode: ;1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2) ;0 = Disables serial port and configures these pins as I/O port pins ;In I2 C mode: ;1 = Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins(3) ;0 = Disables serial port and configures these pins as I/O port pins ;bit 4 CKP: Clock Polarity Select bit ;In SPI mode: ;1 = Idle state for clock is a high level ;0 = Idle state for clock is a low level ;In I2 C Slave mode: SCLx release control ;1 = Enable clock ;0 = Holds clock low (clock stretch). (Used to ensure data setup time.) ;In I2 C Master mode: ;Unused in this mode ;bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits ;0000 = SPI Master mode, clock = FOSC/4 ;0001 = SPI Master mode, clock = FOSC/16 ;0010 = SPI Master mode, clock = FOSC/64 ;0011 = SPI Master mode, clock = TMR2 output/2 ;0100 = SPI Slave mode, clock = SCKx pin, SS pin control enabled ;0101 = SPI Slave mode, clock = SCKx pin, SS pin control disabled, SSx can be used as I/O pin ;0110 = I2C Slave mode, 7-bit address ;0111 = I2C Slave mode, 10-bit address ;1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD+1))(4) ;1001 = Reserved ;1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))(5) ;1011 = I2C firmware controlled Master mode (Slave idle) ;1100 = Reserved ;1101 = Reserved ;1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled ;1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled BANKSEL SSP1CON1 MOVLW B'00000000' MOVWF SSP1CON1 BANKSEL APFCON BCF APFCON,SDOSEL ;ADATKIMENET AZ RC2 ;SSPCON3 ; bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) ; 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCLx clock ; 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCLx clock ; bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) ; 1 = Enable interrupt on detection of Stop condition ; 0 = Stop detection interrupts are disabled(2) ; bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) ; 1 = Enable interrupt on detection of Start or Restart conditions ; 0 = Start detection interrupts are disabled(2) ; bit 4 BOEN: Buffer Overwrite Enable bit ; In SPI Slave mode:(1) ; 1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit ; 0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the ; SSPxCON1 register is set, and the buffer is not updated ; In I2C Master mode: ; This bit is ignored. ; In I2C Slave mode: ; 1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the ; state of the SSPOV bit only if the BF bit = 0. ; 0 = SSPxBUF is only updated when SSPOV is clear ; bit 3 SDAHT: SDAx Hold Time Selection bit (I2C mode only) ; 1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx ; 0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx ; bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) ; If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the ; BCLxIF bit of the PIR2 register is set, and bus goes idle ; 1 = Enable slave bus collision interrupts ; 0 = Slave bus collision interrupts are disabled ; bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) ; 1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the ; SSPxCON1 register will be cleared and the SCLx will be held low. ; 0 = Address holding is disabled ; bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) ; 1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit ; of the SSPxCON1 register and SCLx is held low. ; 0 = Data holding is disabled BANKSEL SSP1CON3 MOVLW B'11101111' ;SSPSTAT ; bit 7 SMP: SPI Data Input Sample bit ; SPI Master mode: ; 1 = Input data sampled at end of data output time ; 0 = Input data sampled at middle of data output time ; SPI Slave mode: SMP must be cleared when SPI is used in Slave mode ; In I2 C Master or Slave mode: ; 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) ; 0 = Slew rate control enabled for high speed mode (400 kHz) ; bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) ; In SPI Master or Slave mode: ; 1 = Transmit occurs on transition from active to Idle clock state ; 0 = Transmit occurs on transition from Idle to active clock state ; In I2 C™ mode only: ; 1 = Enable input logic so that thresholds are compliant with SMBus specification ; 0 = Disable SMBus specific inputs ; bit 5 D/A: Data/Address bit (I2C mode only) ; 1 = Indicates that the last byte received or transmitted was data ; 0 = Indicates that the last byte received or transmitted was address ; bit 4 P: Stop bit ; (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPEN is cleared.) ; 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) ; 0 = Stop bit was not detected last ; bit 3 S: Start bit ; (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPEN is cleared.) ; 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) ; 0 = Start bit was not detected last ; bit 2 R/W: Read/Write bit information ; (I2C mode only) ; This bit holds the R/W bit information following the last address match. This bit is only valid from the address match ; to the next Start bit, Stop bit, or not ACK bit. ; In I2 C Slave mode: ; 1 = Read ; 0 = Write ; In I2 C Master mode: ; 1 = Transmit is in progress ; 0 = Transmit is not in progress ; OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode. ; bit 1 UA: Update Address bit ; (10-bit I2C mode only) ; 1 = Indicates that the user needs to update the address in the SSPxADD register ; 0 = Address does not need to be updated ; bit 0 BF: Buffer Full Status bit ; Receive (SPI and I2 C modes): ; 1 = Receive complete, SSPxBUF is full ; 0 = Receive not complete, SSPxBUF is empty ; Transmit (I2 C mode only): ; 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full ; 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty BANKSEL SSP1STAT MOVLW B'11111111' ; T2CON ; bit 7 Unimplemented: Read as ‘0’ ; bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits ; 0000 = 1:1 Postscaler ; 0001 = 1:2 Postscaler ; 0010 = 1:3 Postscaler ; 0011 = 1:4 Postscaler ; 0100 = 1:5 Postscaler ; 0101 = 1:6 Postscaler ; 0110 = 1:7 Postscaler ; 0111 = 1:8 Postscaler ; 1000 = 1:9 Postscaler ; 1001 = 1:10 Postscaler ; 1010 = 1:11 Postscaler ; 1011 = 1:12 Postscaler ; 1100 = 1:13 Postscaler ; 1101 = 1:14 Postscaler ; 1110 = 1:15 Postscaler ; 1111 = 1:16 Postscaler ; bit 2 TMR2ON: Timer2 On bit ; 1 = Timer2 is on ; 0 = Timer2 is off ; bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits ; 00 = Prescaler is 1 ; 01 = Prescaler is 4 ; 10 = Prescaler is 16 ; 11 = Prescaler is 64 ;T1CON ; bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits ; 11 =Timer1 clock source is LFINTOSC ; 10 =Timer1 clock source is T1CKI pin (on rising edge) ; 01 =Timer1 clock source is system clock (FOSC) ; 00 =Timer1 clock source is instruction clock (FOSC/4) ; bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits ; 11 = 1:8 Prescale value ; 10 = 1:4 Prescale value ; 01 = 1:2 Prescale value ; 00 = 1:1 Prescale value ; bit 3 Unimplemented: Read as ‘0’ ; bit 2 T1SYNC: Timer1 Synchronization Control bit ; 1 = Do not synchronize asynchronous clock input ; 0 = Synchronize asynchronous clock input with system clock (FOSC) ; bit 1 Unimplemented: Read as ‘0’ ; bit 0 TMR1ON: Timer1 On bit ; 1 = Enables Timer1 ; 0 = Stops Timer1 and clears Timer1 gate flip-flop BANKSEL T1CON ;LFINTOSC BEMENET /8 MOVLW B'11110001' MOVWF T1CON ; T1GCON ; bit 7 TMR1GE: Timer1 Gate Enable bit ; If TMR1ON = 0: ; This bit is ignored ; If TMR1ON = 1: ; 1 = Timer1 counting is controlled by the Timer1 gate function ; 0 = Timer1 counts regardless of Timer1 gate function ; bit 6 T1GPOL: Timer1 Gate Polarity bit ; 1 = Timer1 gate is active-high (Timer1 counts when gate is high) ; 0 = Timer1 gate is active-low (Timer1 counts when gate is low) ; bit 5 T1GTM: Timer1 Gate Toggle Mode bit ; 1 = Timer1 Gate Toggle mode is enabled ; 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared ; Timer1 gate flip-flop toggles on every rising edge. ; bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit ; 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate ; 0 = Timer1 gate Single-Pulse mode is disabled ; bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit ; 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge ; 0 = Timer1 gate single-pulse acquisition has completed or has not been started ; bit 2 T1GVAL: Timer1 Gate Current State bit ; Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. ; Unaffected by Timer1 Gate Enable (TMR1GE). ; bit 0 T1GSS<1:0>: Timer1 Gate Source Select bits ; 11 = Comparator 2 optionally synchronized output (sync_C2OUT) ; 10 = Comparator 1 optionally synchronized output (sync_C1OUT) ; 01 = Timer0 overflow output ; 00 = Timer1 gate pin BANKSEL T1GCON MOVLW B'00000000' MOVWF T1GCON BANKSEL PIE1 BSF PIE1,TMR1IE BANKSEL PIR1 BSF PIR1,TMR1IF MOVLW 0X20 MOVWF FSR1H ;FELSŐ FÉL BEÁLLÍTÁSA MEMÓRIA OLVASÁSRA ;--------------------------------------------------------------------- ; ; FŐPROGRAM ; ;---------------------------------------------------------------------- ; LED 0,PI,0X01 ; LED 0,ZO,0X01 ; LED 0,KE, 0X02 ; LED 1,PI,0X02 ; LED 2,PI,0X04 ; LED 3,PI,0X08 ; LED D'58',PI,0X0F ; LED D'59',PI,0X01 VV BTFSS KIJ BRA VV BCF KIJ CALL DISP BRA VV LED_K MOVFW NUM ;FÉLBYTE KISZAMOLÁSA ADDWF NUM,W ADDWF NUM,W RRF WREG MOVWF FSR1L BTFSS STATUS,C BRA PAROS ZOLD_L ; INCF FSR1L ;NEM NULLÁVAL KEZD BTFSS ZOLD BRA PIROS_L INCF FSR1L MOVFW LUME SWAPF WREG,F IORWF INDF1,F ;FELSŐ BYTE ALSÓ FELE A ZÖLD BRA RET PIROS_L BTFSS PIROS BRA KEK_L INCF FSR1L MOVFW LUME IORWF INDF1,F BRA RET KEK_L BTFSS KEK BRA RET MOVFW LUME SWAPF WREG,F IORWF INDF1,F BRA RET PAROS ZOLD_H INCF FSR1L ;LAP KEZDETE BTFSS ZOLD BRA PIROS_H INCF FSR1L MOVFW LUME IORWF INDF1,F ;FÉNY A HELYÉRE BRA RET PIROS_H BTFSS PIROS BRA KEK_H MOVFW LUME SWAPF WREG,F IORWF INDF1,F BRA RET KEK_H BTFSS KEK BRA RET MOVFW LUME IORWF INDF1,F BRA RET RET RETURN DISP MOVLW 20 MOVWF FSR1H MOVLW 0X5A MOVWF FSR1L ;MUTATÓ AZ ELEJÉRE BANKSEL INTCON BCF INTCON,GIE ;MEGSZAKÍTÁS TILTÁSA BANKSEL PORTC BRA IND2 ;KEZDŐ CSALÁS IND BCF PORTC,0 IND2 BSF PORTC,0 ;1 BIT RLF INDF1 ;BIT_1 RLF PORTC ;KIKÜLDVE A PORTRA RLF INDF1 ;BIT_2 KIOLVASÁSA BCF PORTC,0 ;ADAT VÉGE NOP ;A BÉKE KEDVÉÉRT BSF PORTC,0 ;2. BIT RLF PORTC ;BIT KIKÜLDÉSE RLF INDF1 ;BIT_3 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;3. BIT RLF PORTC ;BIT KIKÜLDÉSE RLF INDF1 ;BIT_4 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;4. BIT RLF PORTC ;BIT KIKÜLDÉSE CLRC ;BIT_5 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;5. BIT RLF PORTC ;BIT KIKÜLDÉSE CLRC ;BIT_6 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;6. BIT RLF PORTC ;BIT KIKÜLDÉSE CLRC ;BIT_7 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;7. BIT RLF PORTC ;BIT KIKÜLDÉSE CLRC ;BIT_8 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;2. BIT RLF PORTC ;BIT KIKÜLDÉSE RLF INDF1 ;BIT_3 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;3. BIT RLF PORTC ;BIT KIKÜLDÉSE RLF INDF1 ;BIT_4 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;4. BIT RLF PORTC ;BIT KIKÜLDÉSE RLF INDF1 ;BIT_5 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;5. BIT RLF PORTC ;BIT KIKÜLDÉSE RLF INDF1 ;BIT_6 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;2. BIT RLF PORTC ;BIT KIKÜLDÉSE CLRC ;BIT_3 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;3. BIT RLF PORTC ;BIT KIKÜLDÉSE CLRC ;BIT_4 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;4. BIT RLF PORTC ;BIT KIKÜLDÉSE CLRC ;BIT_5 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;5. BIT RLF PORTC ;BIT KIKÜLDÉSE CLRC ;BIT_6 KIOLVASÁSA BCF PORTC,0 NOP BSF PORTC,0 ;8. BIT 50 RLF PORTC ;BIT KIKÜLDÉSE 75 DECFSZ FSR1L BRA IND BCF PORTC,0 ;KIJELZÉS VÉGE BANKSEL INTCON BSF INTCON,GIE ;MEGSZAKÍTÁS ENGEDÉLYEZÉSE RETURN END