// ENC28J60 Stand-Alone Ethernet Controller with SPI Interface (MICROCHIP)

#define		RCR			0b00000000		// Read Control Register
#define		RBM			0b00111010		// Read Buffer Memory
#define		WCR			0b01000000		// Write Control Register
#define		WBM			0b01111010		// Write Buffer Memory 
#define		BFS			0b10000000		// Bit Field Set
#define		BFC			0b10100000		// Bit Field Clear
#define		SRC			0b11111111		// System Reset Command (Soft Reset)

// ENC28J60 Cntrl  Reg Map
// all Banks
#define		EIE			0x1B			// 
#define		EIR			0x1C			// 
#define		ESTAT		0x1D			// 
#define		ECON1		0x1F			// ETHERNET CONTROL REGISTER 1
	#define		TXRST		0x80		//
	#define		RXRST		0x40		//
	#define		DMAST		0x20		//
	#define		CSUMEN		0x10		//
	#define		TXRTS		0x08		//
	#define		RXEN		0x04		//
	#define		BSEL1		0x02		//
	#define		BSEL0		0x01		//
// BSEL1:0 = BANK3:1
	#define		BANK3		0x03		//
	#define		BANK2		0x02		//
	#define		BANK1		0x01		//
	#define		BANK0		0x00		//
#define		ECON2		0x1E			// ETHERNET CONTROL REGISTER 2
	#define		AUTONIC		0x80		//
	#define		PKTDEC		0x40		//
	#define		PWRSV		0x20		//
	#define		VRPS		0x08		//
	

// Bank0
#define		ERDPTL		0x00			// 
#define		ERDPTH		0x01			// 
#define		EWRPTL		0x02			// 
#define		EWRPTH		0x03			// 
#define		ETXSTL		0x04			// 
#define		ETXSTH		0x05			// 
#define		ETXNDL		0x06			// 
#define		ETXNDH		0x07			// 
#define		ERXSTL		0x08			// 
#define		ERXSTH		0x09			// 
#define		ERXNDL		0x0A			// 
#define		ERXNDH		0x0B			// 
#define		ERXRDPTL	0x0C			// 
#define		ERXRDPTH	0x0D			// 
#define		ERXWRPTL	0x0E			// 
#define		ERXWRPTH	0x0F			// 
#define		EDMASTL		0x10			//
#define		EDMASTH		0x11			//
#define		EDMANDL		0x12			//
#define		EDMANDH		0x13			//
#define		EDMADSTL	0x14			//
#define		EDMADSTH	0x15			//
#define		EDMACSL		0x16			//
#define		EDMACSH		0x17			//


// Bank 1
#define		EHT0		0x00			// 
#define		EHT1		0x01			// 
#define		EHT2		0x02			// 
#define		EHT3		0x03			// 
#define		EHT4		0x04			// 
#define		EHT5		0x05			// 
#define		EHT6		0x06			// 
#define		EHT7		0x07			// 

#define		EPMM0		0x08			// 
#define		EPMM1		0x09			// 
#define		EPMM2		0x0A			// 
#define		EPMM3		0x0B			// 
#define		EPMM4		0x0C			// 
#define		EPMM5		0x0D			// 
#define		EPMM6		0x0E			// 
#define		EPMM7		0x0F			// 

#define		EPMCSL		0x10			// 
#define		EPMCSH		0x11			// 
#define		EPMOL		0x14			// 
#define		EPMOH		0x15			// 
#define		ERXFCON		0x18			// 
#define		EPKTCNT		0x19			// 

// Bank 2
#define		MACON1		0x00			// 
#define		MACON3		0x02			// 
#define		MACON4		0x03			// 
#define		MABBIPG		0x04			// 
#define		MAIPGL		0x06			// 
#define		MAIPGH		0x07			// 
#define		MACLCON1	0x08			// 
#define		MACLCON2	0x09			// 
#define		MAMXFLL		0x0A			// 
#define		MAMXFLH		0x0B			// 
#define		MICMD		0x12			// 
	#define		MIISCAN		0x02		// 
	#define		MIIRD		0x01		// 
#define		MIREGADR	0x00			// 
#define		MIWRL		0x00			// 
#define		MIWRH		0x00			// 
#define		MIRDL 		0x00			// 
#define		MIRDH 		0x00			// 


// Bank 3
#define		MAADR1		0x04			// 
#define		MAADR2		0x05			// 
#define		MAADR3		0x02			// 
#define		MAADR4		0x03			// 
#define		MAADR5		0x00			// 
#define		MAADR6		0x01			// 
#define		EBSTSD		0X06			// 
#define		EBSTCON		0X07			// 
#define		EBSTCSL		0X08			// 
#define		EBSTCSH		0X09			// 
#define		MISTAT		0X0A			// 
	#define		NVALID		0x03		// 
	#define		SCAN		0x02		// 
	#define		BUSY		0x01		// 
#define		EREVID		0X12			// 
#define		ECOCON		0X15			//
#define		EFLOCON		0X17			// 
#define		EPAUSL		0X18			// 
#define		EPAUSH		0X19			// 


volatile unsigned char myIP[4] 		=	{192,	168,	1,		1};
volatile unsigned char myMASK[4] 	=	{255,	255,	255,	255};
volatile unsigned char myMAC[6] 	=	{0x01,	0x23,	0x45,	0x67,	0x89,	0xAB};
volatile unsigned char myLINK[]		=	"http:\\192.168.1.1";
volatile unsigned char myGW[4] 		=	{192,	168,	0,		1};						// router's IP
volatile unsigned char myDNS[4] 	=	{192,	168,	1,		1};

volatile unsigned char PWRD[]		=	"!=~C0d3#";			// !=~C0d3#

unsigned char Net_Buffer;
/*
//SPI_PORT |= (1<<ENC28J60);		// Disable
void ENC28J60_CS(void)				// ENC28J60 Select
{
	SPI_PORT &= ~(1<<ENC28J60);
}

void ENC28J60_DS(void)				// ENC28J60 DeSelect
{
	SPI_PORT |= (1<<ENC28J60);
}

void ENC28J60(unsigned char OPCODE, unsigned char ARGUMENT)
{
	SPI_PORT &= ~(1<<ENC28J60);	// Enable
	SPIWR(OPCODE|ARGUMENT);
}
void ENC28J60_RCR(unsigned char ARGUMENT)	// Read Control Register
{
	SPI_PORT &= ~(1<<ENC28J60);
	SPIWR(ARGUMENT);
}
void ENC28J60_RBM(void)				// Read Buffer Memory
{
	SPI_PORT &= ~(1<<ENC28J60);
	SPIWR(RBM);
	
}
void ENC28J60_WCR(unsigned char ARGUMENT)	// Write Control Register
{
	SPI_PORT &= ~(1<<ENC28J60);
	SPIWR(0x40|ARGUMENT);
}
void ENC28J60_WBM(void)				// Write Buffer Memory 
{
	
}
void ENC28J60_BFS(void)				// Bit Field Set
{
	
}
void ENC28J60_BFC(void)				// Bit Field Clear
{
	
}
void ENC28J60_SRC(void)				// System Reset Command (Soft Reset) 
{
	SPI_PORT &= ~(1<<ENC28J60);	// Enable
	SPIWR(0xFF);
	SPI_PORT |= (1<<ENC28J60);		// Disable
}
void ENC28J60_ETH_RD(unsigned char ARGUMENT)
{
	SPI_PORT &= ~(1<<ENC28J60);
	SPIWR(ARGUMENT);
}
void ENC28J60_RCR(void)
{
	ENC28J60_CS();
	SPIWR(RCR|ERDPTL);
}

void ENC28J60_Init(unsigned char *myMAC, unsigned char *myIP)
{
	//	receive buffer start address : 0x0000.
	ENC28J60_CS();
	SPIWR(WCR|);
	//	receive buffer end address	 : 0x19AD.
	//	transmit buffer start address: 0x19AE.
	//	transmit buffer end address	 : 0x1FFF.
	//	RAM buffer read/write pointers in auto-increment mode.
	//	receive filters set to default: CRC + MAC Unicast + MAC Broadcast in OR mode.
	//	flow control with TX and RX pause frames in full duplex mode.
	//	frames are padded to 60 bytes + CRC.
	//	maximum packet size is set to 1518.
	//	Back-to-Back Inter-Packet Gap: 0x15 in full duplex mode; 0x12 in half duplex mode.
	//	Non-Back-to-Back Inter-Packet Gap: 0x0012 in full duplex mode; 0x0C12 in half duplex mode.
	//	Collision window is set to 63 in half duplex mode to accomodate some ENC28J60 revisions silicon bugs.
	//	CLKOUT output is disabled to reduce EMI generation.
	//	half duplex loopback disabled.
	//	LED configuration: default (LEDA-link status, LEDB-link activity).
}
*/