; PIC18F26K80 Configuration Bit Settings

; ASM source line config statements

#include "p18F26K80.inc"

; CONFIG1L
  CONFIG  RETEN = ON            ; VREG Sleep Enable bit (Ultra low-power regulator is Enabled (Controlled by SRETEN bit))
  CONFIG  INTOSCSEL = LOW       ; LF-INTOSC Low-power Enable bit (LF-INTOSC in Low-power mode during Sleep)
  CONFIG  SOSCSEL = HIGH        ; SOSC Power Selection and mode Configuration bits (High Power SOSC circuit selected)
  CONFIG  XINST = OFF           ; Extended Instruction Set (Disabled)

; CONFIG1H
  CONFIG  FOSC = INTIO2         ; Oscillator (Internal RC oscillator)
  CONFIG  PLLCFG = OFF          ; PLL x4 Enable bit (Disabled)
  CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor (Disabled)
  CONFIG  IESO = OFF            ; Internal External Oscillator Switch Over Mode (Disabled)

; CONFIG2L
  CONFIG  PWRTEN = ON           ; Power Up Timer (Enabled)
  CONFIG  BOREN = NOSLP         ; Brown Out Detect (Enabled while active, disabled in SLEEP, SBOREN disabled)
  CONFIG  BORV = 3              ; Brown-out Reset Voltage bits (1.8V)
  CONFIG  BORPWR = ZPBORMV      ; BORMV Power level (ZPBORMV instead of BORMV is selected)

; CONFIG2H
  CONFIG  WDTEN = OFF           ; Watchdog Timer (WDT disabled in hardware; SWDTEN bit disabled)
  CONFIG  WDTPS = 1048576       ; Watchdog Postscaler (1:1048576)

; CONFIG3H
  CONFIG  CANMX = PORTB         ; ECAN Mux bit (ECAN TX and RX pins are located on RB2 and RB3, respectively)
  CONFIG  MSSPMSK = MSK7        ; MSSP address masking (7 Bit address masking mode)
  CONFIG  MCLRE = ON            ; Master Clear Enable (MCLR Enabled, RE3 Disabled)

; CONFIG4L
  CONFIG  STVREN = ON           ; Stack Overflow Reset (Enabled)
  CONFIG  BBSIZ = BB2K          ; Boot Block Size (2K word Boot Block size)

; CONFIG5L
  CONFIG  CP0 = OFF             ; Code Protect 00800-03FFF (Disabled)
  CONFIG  CP1 = OFF             ; Code Protect 04000-07FFF (Disabled)
  CONFIG  CP2 = OFF             ; Code Protect 08000-0BFFF (Disabled)
  CONFIG  CP3 = OFF             ; Code Protect 0C000-0FFFF (Disabled)

; CONFIG5H
  CONFIG  CPB = OFF             ; Code Protect Boot (Disabled)
  CONFIG  CPD = OFF             ; Data EE Read Protect (Disabled)

; CONFIG6L
  CONFIG  WRT0 = OFF            ; Table Write Protect 00800-03FFF (Disabled)
  CONFIG  WRT1 = OFF            ; Table Write Protect 04000-07FFF (Disabled)
  CONFIG  WRT2 = OFF            ; Table Write Protect 08000-0BFFF (Disabled)
  CONFIG  WRT3 = OFF            ; Table Write Protect 0C000-0FFFF (Disabled)

; CONFIG6H
  CONFIG  WRTC = OFF            ; Config. Write Protect (Disabled)
  CONFIG  WRTB = OFF            ; Table Write Protect Boot (Disabled)
  CONFIG  WRTD = OFF            ; Data EE Write Protect (Disabled)

; CONFIG7L
  CONFIG  EBTR0 = OFF           ; Table Read Protect 00800-03FFF (Disabled)
  CONFIG  EBTR1 = OFF           ; Table Read Protect 04000-07FFF (Disabled)
  CONFIG  EBTR2 = OFF           ; Table Read Protect 08000-0BFFF (Disabled)
  CONFIG  EBTR3 = OFF           ; Table Read Protect 0C000-0FFFF (Disabled)

; CONFIG7H
  CONFIG  EBTRB = OFF           ; Table Read Protect Boot (Disabled)

		#define	LED		LATB,0

		cblock	0x060
				t,t1,t2
		endc

		org		0x000
main:
		movlw	0x50
		movwf	OSCCON
		clrf	CCP5CON
		clrf	PORTB
		clrf	LATB
		clrf	TRISB
;		bsf		LED
loop:
;		btg		LED
		movlw	0x0FF
		movwf	LATB
		call	delay
		bra		loop
delay:
		movlw	d'3'
		movwf	t
		clrf	t1
		clrf	t2
del1:
		decfsz	t2,1,1
		bra		del1
		decfsz	t1,1,1
		bra		del1
		decfsz	t,1,1
		bra		del1
		return

		end