;=={INFORMATION}================================================================
;	File:		1wire.asm
;	Project:	
;	Author:		Tamás Nagy
;	Version:	4.5.0
;	Used PIC:	PIC18F26K80
;=={DESCRIPTION}================================================================
;=={SPECIFICATIONS}=============================================================
;=={PROCESSOR + CONFIG}=========================================================

; PIC18F26K80 Configuration Bit Settings

; ASM source line config statements

#include "p18F26K80.inc"

; CONFIG1L
  CONFIG  RETEN = ON            ; VREG Sleep Enable bit (Ultra low-power regulator is Enabled (Controlled by SRETEN bit))
  CONFIG  INTOSCSEL = HIGH      ; LF-INTOSC Low-power Enable bit (LF-INTOSC in High-power mode during Sleep)
  CONFIG  SOSCSEL = HIGH        ; SOSC Power Selection and mode Configuration bits (High Power SOSC circuit selected)
  CONFIG  XINST = OFF           ; Extended Instruction Set (Disabled)

; CONFIG1H
  CONFIG  FOSC = INTIO2         ; Oscillator (Internal RC oscillator)
  CONFIG  PLLCFG = OFF          ; PLL x4 Enable bit (Disabled)
  CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor (Disabled)
  CONFIG  IESO = OFF            ; Internal External Oscillator Switch Over Mode (Disabled)

; CONFIG2L
  CONFIG  PWRTEN = ON           ; Power Up Timer (Enabled)
  CONFIG  BOREN = SBORDIS       ; Brown Out Detect (Enabled in hardware, SBOREN disabled)
  CONFIG  BORV = 3              ; Brown-out Reset Voltage bits (1.8V)
  CONFIG  BORPWR = ZPBORMV      ; BORMV Power level (ZPBORMV instead of BORMV is selected)

; CONFIG2H
  CONFIG  WDTEN = OFF           ; Watchdog Timer (WDT disabled in hardware; SWDTEN bit disabled)
  CONFIG  WDTPS = 1048576       ; Watchdog Postscaler (1:1048576)

; CONFIG3H
  CONFIG  CANMX = PORTB         ; ECAN Mux bit (ECAN TX and RX pins are located on RB2 and RB3, respectively)
  CONFIG  MSSPMSK = MSK7        ; MSSP address masking (7 Bit address masking mode)
  CONFIG  MCLRE = ON            ; Master Clear Enable (MCLR Enabled, RE3 Disabled)

; CONFIG4L
  CONFIG  STVREN = ON           ; Stack Overflow Reset (Enabled)
  CONFIG  BBSIZ = BB2K          ; Boot Block Size (2K word Boot Block size)

; CONFIG5L
  CONFIG  CP0 = OFF             ; Code Protect 00800-03FFF (Disabled)
  CONFIG  CP1 = OFF             ; Code Protect 04000-07FFF (Disabled)
  CONFIG  CP2 = OFF             ; Code Protect 08000-0BFFF (Disabled)
  CONFIG  CP3 = OFF             ; Code Protect 0C000-0FFFF (Disabled)

; CONFIG5H
  CONFIG  CPB = OFF             ; Code Protect Boot (Disabled)
  CONFIG  CPD = OFF             ; Data EE Read Protect (Disabled)

; CONFIG6L
  CONFIG  WRT0 = OFF            ; Table Write Protect 00800-03FFF (Disabled)
  CONFIG  WRT1 = OFF            ; Table Write Protect 04000-07FFF (Disabled)
  CONFIG  WRT2 = OFF            ; Table Write Protect 08000-0BFFF (Disabled)
  CONFIG  WRT3 = OFF            ; Table Write Protect 0C000-0FFFF (Disabled)

; CONFIG6H
  CONFIG  WRTC = OFF            ; Config. Write Protect (Disabled)
  CONFIG  WRTB = OFF            ; Table Write Protect Boot (Disabled)
  CONFIG  WRTD = OFF            ; Data EE Write Protect (Disabled)

; CONFIG7L
  CONFIG  EBTR0 = OFF           ; Table Read Protect 00800-03FFF (Disabled)
  CONFIG  EBTR1 = OFF           ; Table Read Protect 04000-07FFF (Disabled)
  CONFIG  EBTR2 = OFF           ; Table Read Protect 08000-0BFFF (Disabled)
  CONFIG  EBTR3 = OFF           ; Table Read Protect 0C000-0FFFF (Disabled)

; CONFIG7H
  CONFIG  EBTRB = OFF           ; Table Read Protect Boot (Disabled)

;=={DEFINITIONS}================================================================
;--{I/O PORTS}------------------------------------------------------------------
;--{CONSTANTS}------------------------------------------------------------------
;--{VARIABLES}------------------------------------------------------------------
     cblock    0x000
               W_TEMP, STATUS_TEMP,BSR_TEMP
               t,t1,t2,t3
     endc
;--{MACROES}--------------------------------------------------------------------
;==(PROGRAM START)==============================================================
	 org	   0x000	 ; start vector
     goto      main
;=={HIGH PRIORITY INTERRUPT VECTOR}=============================================
	 org	   0x008
     goto      ISR_CODE
;=={LOW PRIORITY INTERRUPT VECTOR}==============================================
;	 org	   0x018
;//{MAIN}\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
main:
     movlw     0x70
     movwf     OSCCON

     bcf       INTCON2,RBPU

     clrf      ANCON1
     clrf      CM1CON

     clrf      PORTB
     clrf      LATB
     movlw     0x01
     movwf     TRISB

     clrf      PORTC
     clrf      LATC
     clrf      TRISC

     bcf       INTCON,INT0IF
     bsf       INTCON,INT0IE
     bcf       INTCON2,INTEDG0

main_loop:
     nop
     movlw     d'5'
     call      delay_100ms
     bcf       LATC,RC6
     sleep
     goto      main_loop

ISR_CODE:
     bcf       INTCON,INT0IF
     movff     WREG,W_TEMP         ; W_TEMP is in virtual bank
     MOVFF     STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
     MOVFF     BSR, BSR_TEMP       ; BSR_TMEP located anywhere

     bsf       LATC,RC6

     MOVFF     BSR_TEMP, BSR       ; Restore BSR
     MOVF      W_TEMP,W           ; Restore WREG
     MOVFF     STATUS_TEMP, STATUS ; Restore STATUS
     retfie
;=={SUBROUTINES}================================================================
     #include  "delay16MHz.inc"
;=={END Program}================================================================
	 end