;**********************************************************
;
;
;******************Inicializálás***************************

	LIST	P=PIC18F6622
	INCLUDE	<P18F6622.INC>
	
;   Oscillator Selection bits:
;     CONFIG OSC = LP             LP oscillator
;     CONFIG OSC = XT             XT oscillator
;     CONFIG OSC = HS             HS oscillator
;     CONFIG OSC = RC             External RC oscillator, CLKO function on RA6
;     CONFIG OSC = EC             EC oscillator, CLKO function on RA6
;     CONFIG OSC = ECIO6          EC oscillator, port function on RA6
;     CONFIG OSC = HSPLL          HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
;     CONFIG OSC = RCIO6          External RC oscillator, port function on RA6
 	  CONFIG OSC = INTIO67        ;Internal oscillator block, port function on RA6 and RA7
;     CONFIG OSC = INTIO7         Internal oscillator block, CLKO function on RA6, port function on RA7
;
;   Fail-Safe Clock Monitor Enable bit:
     CONFIG FCMEN = OFF          ;Fail-Safe Clock Monitor disabled
;     CONFIG FCMEN = ON           Fail-Safe Clock Monitor enabled
;
;   Internal/External Oscillator Switchover bit:
;     CONFIG IESO = OFF           Two-Speed Start-up disabled
;     CONFIG IESO = ON            Two-Speed Start-up enabled
;
;   Power-up Timer Enable bit:
;     CONFIG PWRT = ON            PWRT enabled
     CONFIG PWRT = OFF           ;PWRT disabled
;
;   Brown-out Reset Enable bits:
     CONFIG BOREN = OFF          ;Brown-out Reset disabled in hardware and software
;     CONFIG BOREN = ON           Brown-out Reset enabled and controlled by software (SBOREN is enabled)
;     CONFIG BOREN = NOSLP        Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
;     CONFIG BOREN = SBORDIS      Brown-out Reset enabled in hardware only (SBOREN is disabled)
;
;   Brown-out Voltage bits:
;     CONFIG BORV = 0             Maximum setting
;     CONFIG BORV = 1             
;     CONFIG BORV = 2             
;     CONFIG BORV = 3             Minimum setting
;
;   Watchdog Timer:
     CONFIG WDT = OFF            ;WDT disabled (control is placed on the SWDTEN bit)
;     CONFIG WDT = ON             WDT enabled
;
;   Watchdog Timer Postscale Select bits:
;     CONFIG WDTPS = 1            1:1
;     CONFIG WDTPS = 2            1:2
;     CONFIG WDTPS = 4            1:4
;     CONFIG WDTPS = 8            1:8
;     CONFIG WDTPS = 16           1:16
;     CONFIG WDTPS = 32           1:32
;     CONFIG WDTPS = 64           1:64
;     CONFIG WDTPS = 128          1:128
;     CONFIG WDTPS = 256          1:256
;     CONFIG WDTPS = 512          1:512
;     CONFIG WDTPS = 1024         1:1024
;     CONFIG WDTPS = 2048         1:2048
;     CONFIG WDTPS = 4096         1:4096
;     CONFIG WDTPS = 8192         1:8192
;     CONFIG WDTPS = 16384        1:16384
;     CONFIG WDTPS = 32768        1:32768
;
;   CCP2 MUX bit:
;     CONFIG CCP2MX = PORTE       ECCP2 input/output is multiplexed with RE7
;     CONFIG CCP2MX = PORTC       ECCP2 input/output is multiplexed with RC1
;
;   Low-Power Timer1 Oscillator Enable bit:
;     CONFIG LPT1OSC = OFF        Timer1 configured for higher power operation
;     CONFIG LPT1OSC = ON         Timer1 configured for low-power operation
;
;   MCLR Pin Enable bit:
     CONFIG MCLRE = OFF          ;RG5 input pin enabled; MCLR disabled
;     CONFIG MCLRE = ON           MCLR pin enabled; RG5 input pin disabled
;
;   Stack Full/Underflow Reset Enable bit:
;     CONFIG STVREN = OFF         Stack full/underflow will not cause Reset
;     CONFIG STVREN = ON          Stack full/underflow will cause Reset
;
;   Single-Supply ICSP Enable bit:
;     CONFIG LVP = OFF            Single-Supply ICSP disabled
;     CONFIG LVP = ON             Single-Supply ICSP enabled
;
;   Boot Block Size Select bits:
;     CONFIG BBSIZ = BB2K         1K word (2 Kbytes) Boot Block size
;     CONFIG BBSIZ = BB4K         2K words (4 Kbytes) Boot Block size
;     CONFIG BBSIZ = BB8K         4K words (8 Kbytes) Boot Block size
;
;   Extended Instruction Set Enable bit:
;     CONFIG XINST = OFF          Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
;     CONFIG XINST = ON           Instruction set extension and Indexed Addressing mode enabled
;
;   Background Debugger Enable bit:
;     CONFIG DEBUG = ON           Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
;     CONFIG DEBUG = OFF          Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
;
;   Code Protection bit Block 0:
;     CONFIG CP0 = ON             Block 0 (000800, 001000 or 002000-003FFFh) code-protected
;     CONFIG CP0 = OFF            Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
;
;   Code Protection bit Block 1:
;     CONFIG CP1 = ON             Block 1 (004000-007FFFh) code-protected
;     CONFIG CP1 = OFF            Block 1 (004000-007FFFh) not code-protected
;
;   Code Protection bit Block 2:
;     CONFIG CP2 = ON             Block 2 (008000-00BFFFh) code-protected
;     CONFIG CP2 = OFF            Block 2 (008000-00BFFFh) not code-protected
;
;   Code Protection bit Block 3:
;     CONFIG CP3 = ON             Block 3 (00C000-00FFFFh) code-protected
;     CONFIG CP3 = OFF            Block 3 (00C000-00FFFFh) not code-protected
;
;   Boot Block Code Protection bit:
;     CONFIG CPB = ON             Boot Block (000000-0007FFh) code-protected
;     CONFIG CPB = OFF            Boot Block (000000-0007FFh) not code-protected
;
;   Data EEPROM Code Protection bit:
;     CONFIG CPD = ON             Data EEPROM code-protected
;     CONFIG CPD = OFF            Data EEPROM not code-protected
;
;   Write Protection bit Block 0:
;     CONFIG WRT0 = ON            Block 0 (000800, 001000 or 002000-003FFFh) write-protected
;     CONFIG WRT0 = OFF           Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
;
;   Write Protection bit Block 1:
;     CONFIG WRT1 = ON            Block 1 (004000-007FFFh) write-protected
;     CONFIG WRT1 = OFF           Block 1 (004000-007FFFh) not write-protected
;
;   Write Protection bit Block 2:
;     CONFIG WRT2 = ON            Block 2 (008000-00BFFFh) write-protected
;     CONFIG WRT2 = OFF           Block 2 (008000-00BFFFh) not write-protected
;
;   Write Protection bit Block 3:
;     CONFIG WRT3 = ON            Block 3 (00C000-00FFFFh) write-protected
;     CONFIG WRT3 = OFF           Block 3 (00C000-00FFFFh) not write-protected
;
;   Configuration Register Write Protection bit:
;     CONFIG WRTC = ON            Configuration registers (300000-3000FFh) write-protected
;     CONFIG WRTC = OFF           Configuration registers (300000-3000FFh) not write-protected
;
;   Boot Block Write Protection bit:
;     CONFIG WRTB = ON            Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected
;     CONFIG WRTB = OFF           Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
;
;   Data EEPROM Write Protection bit:
;     CONFIG WRTD = ON            Data EEPROM write-protected
;     CONFIG WRTD = OFF           Data EEPROM not write-protected
;
;   Table Read Protection bit Block 0:
;     CONFIG EBTR0 = ON           Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks
;     CONFIG EBTR0 = OFF          Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
;
;   Table Read Protection bit Block 1:
;     CONFIG EBTR1 = ON           Block 1 (004000-007FFFh) protected from table reads executed in other blocks
;     CONFIG EBTR1 = OFF          Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
;
;   Table Read Protection bit Block 2:
;     CONFIG EBTR2 = ON           Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
;     CONFIG EBTR2 = OFF          Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
;
;   Table Read Protection bit Block 3:
;     CONFIG EBTR3 = ON           Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
;     CONFIG EBTR3 = OFF          Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
;
;   Boot Block Table Read Protection bit:
;     CONFIG EBTRB = ON           Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks
;     CONFIG EBTRB = OFF          Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
	
;********************Változók******************************

	CBLOCK
		count
		count1
		counta
		countb	
	ENDC
	
;*******************Megszakítás****************************

;	ORG
	
;******************Főprogram*******************************

	ORG 0x0000
	goto	Setup
	
Setup
	movlw	b'00000010'
	movwf	OSCCON
	clrf	PORTA
	clrf	LATA
	clrf	TRISA
	clrf	PORTB
	clrf	LATB
	clrf	TRISB
	clrf	PORTC
	clrf	LATC
	clrf	TRISC
	clrf	PORTD
	clrf	LATD
	clrf	TRISD
	clrf	PORTE
	clrf	LATE
	clrf	TRISE
	clrf	PORTF
	clrf	LATF
	clrf	TRISF
	clrf	PORTG
	clrf	LATG
	clrf	TRISG
	movlw	b'00001111'
	movwf	ADCON1
	
Start	
	incf	LATG
	call	Kesleltet255
	goto	Start
	
	
;******************Szubrutinok*****************************
Kesleltet255
     movlw   0xff             ; A késleltetés 255ms.
     goto    K0
Kesleltet100
     movlw   d'100'           ; A késleltetés 100ms.
     goto    K0
Kesleltet50
     movlw   d'50'            ; A késleltetés 50ms.
     goto    K0
Kesleltet20
     movlw   d'20'            ; A késleltetés 20ms.
     goto    K0
Kesleltet5
     movlw   0x05             ; A késleltetés 5.000 ms (4 MHz órajel).
K0
     movwf   count1
K1
     movlw   0xC7             ; A késleltetés 1ms.
     movwf   counta
     movlw   0x01
     movwf   countb
Kesleltet_0
     decfsz  counta,f
     goto    Kesleltet_0
     decfsz  countb,f
     goto    Kesleltet_0

     decfsz  count1,f
     goto    K1
     retlw   0x00

	END
	
	