<h3>SparkFun Electronics' preferred foot prints</h3> In this library you'll find non-functional items- supply symbols, logos, notations, frame blocks, etc.<br><br> We've spent an enormous amount of time creating and checking these footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com. <br><br> <b>Licensing:</b> Creative Commons ShareAlike 4.0 International - https://creativecommons.org/licenses/by-sa/4.0/ <br><br> You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage. Released under the Creative Commons Attribution Share-Alike 4.0 License https://creativecommons.org/licenses/by-sa/4.0/ Designed by: This is half of a tab, with fiducial reference mark, used to connect individual boards in a panel of PCBs. Two of these half tabs, rotated in opposite directions, can be connected together to form a full tab, with two fiducial markings. Place along the edge of a panel of PCBs, this will allow for panels with boards not connected by v-scores, which allows for easier depanelization where there are overhanging components. It can also be used for designs too small to accomodate fiducial marks on individual boards. >NAME >VALUE IOIO-OTG label with exposed copper THIS IS A FOUR-LAYER BOARD! Revision By: Breadboard row spacing: ES Released under the Creative Commons Attribution Share-Alike 3.0 License http://creativecommons.org/licenses/by-sa/3.0 Design by: >VALUE FIO_LOGO Fabrickit logo Fabrickit logotype A B C D E F G H 1 2 3 4 5 H G F E D C B A 5 4 3 2 1 >DRAWING_NAME >LAST_DATE_TIME >SHEET Drawn By: Title: Version: Date: >LAST_DATE_TIME Sheet: >SHEET REV: TITLE: >DRAWING_NAME Released under the Creative Commons Attribution Share-Alike 4.0 License https://creativecommons.org/licenses/by-sa/4.0/ Design by: FIRST OTL SFE File Names 1. Directory names will be: "Thingy" 1. No version number or production variation like 'Thingy with Chip Antenna' 2. File names are 1. Thingy-v10.sch 2. Thingy-v10.brd 3. Panel names are: Thingy-Panel-v10.brd 4. Minor versions are: Thingy-v11, v12, v13 5. Major versions are v10, v20, v30. 6. Prototypes/New Products start in the sandbox then migrate to the store front specific category once listed in the storefront. Schematic Layout 1. All parts stay on a 0.1" grid. Do not violate this rule. 2. All GND connections use the GND symbol. 3. All VCC, 5V, 3.3V etc. will use the appropriate power symbol. 4. Name all components with standard names (No dollars signs allowed!): 1. U# - ICs 2. Q# - Transistors 3. R#/C#/L# - Resistors/Capacitors/Inductors 4. Y# - Antennas and Crystals/Resonators 5. D# - LEDs and Diodes 6. S# - Switches 7. JP# - Connectors and Headers 8. 'U$3' is bad. If a part automatically puts a "$" in the name, it needs to be fixed. 5. Every schematic will have the part FRAME-LETTER added to it. 6. Use two fiducials on each board where applicable. Use your judgement. Small boards (less than 1x1") can skip this rule. 1. Add the part FIDUCIAL to the schematic. It's OK to use the smallest 1x2mm footprint. 7. If board is larger than 1", then seriously consider standoffs. Use your judgement. 1. Add part STANDOFF to the schematic. This part has a keepout layer to show you where the head of the standoff screw will be. 8. Add fiducials, standoff components and logo box to the lower right area of the schematic sheet. 9. Use dashed gray lines to separate a complex design into various smaller bits. 1. For example: charge circuit, accelerometer, microcontroller, etc. PCB Layout 1. Create the board frame on a 0.1" grid. 1. Make the lower left corner start at 0,0. 2. Change the line width of the board frame to .008" 3. Board frame will be square unless called for by special requirements of the design. 5. All parts are place on a 0.05" grid. You may not break this rule unless you have a very good reason. 6. Use 10 mil (0.010") traces. 1. 8 mil traces can be used when necessary, 7 mil is absolute minimum. 2. Use thicker traces (as thick as possible) on power and charging traces. 1. 10 mil = 100mA 2. 12 mil = 500mA 7. Keep at least 8 mil of space between traces. 8. Route with straight lines and 45 degree corners. 1. Avoid 90 degree corners. 9. Route from the center of pads. Avoid routing into the pads - this causes traces to be not centered on a pad. 10. If something is soldered into a hole (header, connector, prototype vias, etc), use a via with a larger annular ring so that it is easier to solder. 11. Use ground pours on the top and bottom layers. 1. Change the Isolate setting on ground pours to 12 mil (0.012"). 12. Set the default via size to 0.020." 1. 0.015 is the smallest allowed via size. Only change from the default if absolutely necessary. 2. Tip: Via size is defined by the Drill parameter. 13. Add a Date Code on the bottom layer of the board 1. Revise the Date code on every minor and major revision! 14. In the PCB Layout Editor use the following colors: 1. White for top silkscreen (tPlace) 2. Yellow for bottom silkscreen (bPlace) 3. Mellow Yellow for tDocu 15. Every board should have the full SparkFun logo or at least the smaller SFE Flame 1. To do this, add the LOGO-SFE part to the schematic. Make sure to put this part in the lower right hand corner of the schematic. 16. Components that are grouped together in the schematic will be grouped together in the PCB layout. 17. The autorouter can only be used on prototypes. 1. Hand routing and touch-up of the autorouter is expected for production boards. 18. Make sure to load the SparkFun.dru for the DRC check. Don't use the default settings! PCB Aesthetics (Labeling) 2. Label any LED with its purpose (power, status, D4, Lock, etc). 3. Label all connectors (VIN, Port1, Batt, 5-9V, etc). 4. Label pins where applicable (Tx, Rx, Power, +, Charger, etc). 5. Label switches and switch states (On/Off, USB, etc). 6. Makes sure labels are on a straight line 1. Add a line in the tDocu layer to make sure the labels line up. New Footprints 1. All footprints need >Name (on the tNames layer). 1. Size should be 0.016" 2. All footprints need >Value (on the tValues layer). 1. Size should be 0.016" 3. All footprints need silkscreen or tDocu indicators showing mechanical sizes, dimensions or anything weird about the part. 5. Silkscreen within a footprint or board should NOT go over pads or metal that will be exposed. 6. Every new footprint and part will have a description containing part information (SparkFun SKU) and whether the footprint has been proven. 1. Open the library, click on the "device." Select the problem device. Click on "Prefix" button. Type the correct prefix letter. Save and update the library. 1. For normal prototyping vias, use 0.04" hole with a 0.074" diameter (not auto). New Schematic Components 1. All schematic components need >Name and >Value (on the tNames/tValues layer). 1. Size should be 0.07" 2. Pin length on a component should be 'short' unless otherwise needed. 4. If it's a 2-layer board (it should be) then remove all internal layers. 1. See SparkFun tutorial: "Removing Layers in Eagle" 2. Give some space between the >Name and >Value identifier and the component frame. Printing Schematics 2. Select 'Print to file (PDF)' as the printer 3. Make sure 'Rotate' is NOT checked 4. Make sure 'Caption' is NOT checked 5. Select Sheets : 'All' to print all sheets 6. Make sure scale factor is '1' 1. If you see any 'U$2' part indentifiers, do not print. See Schematic Layout rule #4-8. SparkFun Eagle Rules These are the rules that all engineers must follow at SparkFun when designing a PCB. Last updated 4-26-2010 1. All label text sizes will not be smaller than 0.04" for readability. 0.032" is the hard minimum. 0.05" is good and large. 3. Group power pins together on left side of component. Group I/O pins to right side. 4. Group banks of functionally similar pins together (all VCC, all GND, all NCs, I2C, analog, PORTC, etc). 10. Components must have correct values assigned to each part. For example a capacitor value would be: 0.1uF/25V 4. Origin of the footprint must be located in the center of the footprint. Where possible, the footprint should be symmetric on both axises. StarBoard >VALUE >VALUE >VALUE >VALUE >VALUE >VALUE >VALUE >VALUE >VALUE IOIO label THIS IS A FOUR-LAYER BOARD! >NAME Revision By: Isolated power supply >VALUE Isolated ground >VALUE >VALUE >VALUE >VALUE >DRAWING_NAME >LAST_DATE_TIME >SHEET Sheet: >CNAME Rev: >DESIGNER >CREVISION <b>SUPPLY SYMBOL</b> <b>Fiducial Alignment Points</b> Various fiducial points for machine vision alignment. Fiducial/tab for panelizing boards. Logo for the FIO products <h3>Fabrick.it Logos</h3> <h3>Fabrick.it Logotype</h3> <b>Schematic Frame</b><p> Standard 8.5x11 US Letter frame <b>SUPPLY SYMBOL</b> <b>Open Source Hardware Logo</b> This logo indicates the piece of hardware it is found on incorporates a OSHW license and/or adheres to the definition of open source hardware found here: http://freedomdefined.org/OSHW <b>SUPPLY SYMBOL</b> <b>SUPPLY SYMBOL</b> <b>VNEG</b><br> Generic negative voltage terminal. <b>V_BATT</b><br> Generic symbol for the battery input to a system. 1.0V supply symbol 1.8V supply symbol 2.8V supply symbol <b>SUPPLY SYMBOL</b> Vin supply symbol Labels for the IOIO-OTG Warning text which will appear on both the schematic<BR> and the board file, notifying viewers that the design is a<br> four-layer PCB. <h3>SFE Logo, flame only</h3><p> This is the SparkFun flame logo. The logo on the schematic will always be<br> the same size; the package variant is the height of the flame. Default layer<br> for the logo on the board is tSilk. <h3>SFE Logo, name and flame</h3><p> This is the SparkFun full logo. The logo on the schematic will always be<br> the same size; the package variant is the height of the flame part of the<br> logo. Default layer for the logo on the board is tSilk. <h3>SFE Logo, name only</h3><p> This is the SparkFun name logo. The logo on the schematic will always be<br> the same size; the package variant is the height of the flame part of the<br> logo (or the height the flame <b>would</b> be, if it were drawn). Default layer for the logo on the board is tSilk. <b>Schematic Frame</b><p> Standard 11x14 US Ledger frame Logo for the RedBot board. Approx. .5" high, 1.4" wide Isolated power supply Isolated ground <b>SUPPLY SYMBOL</b> SparkFun.com board silk. Logo for the Logomatic boards.<br> Silk is .4" by 1.1"<br> Board logo is .4" by 1.1" <b>Schematic Frame-European Format</b> <br><br> Standard A4 size frame in Landscape Reference markings that correspond to solderless breadboard row spacing.