;Hitachi HD44780 modul kezelő. Az inicializáló rész nincs időzítve oda kell a POR hosszú szünete
.Macro			HD44780	num2, num1, num0
				mov		#0b00000&num2&&num1&0&num0&, W0
				mov		W0, LATD
				bset	LATD, #8		;E = 1		Enable
				nop
				bclr	LATD, #8		;E = 1		Disable
				;repeat	#
				nop
.Endm				
;Interrupt Handler for HD44870 LCD service routine using Timer2 for 40ms (25 pic/s) refresh rate
__T1Interrupt:		bclr	IFS0, #3		;Clear Timer1 Interrupt Flag
					bclr	T1CON, #15		;Timer1 OFF
					call	RefreshDisplay
					clr		TMR1			;Clear Timer1 Counter
					bset	T1CON, #15		;Timer1 ON					
					retfie
;Initialize HD44780 module: Before this long Delay Needed
HD44780init:	clr		TRISD		;PORT.D output
				clr		LATD		;PORT.D = 0x0000
;							Char/Command,	R/W,	Data
				HD44780		0,				0,		00111000	;8 bit Databus 2(4) Line, 5x7 characters	
				HD44780		0,				0,		00001111	;Display on, Underline, Blink
				HD44780		0,				0,		00000001	;Clear Display
				HD44780		0,				0,		00000010	;Display & Cursor Home
;--------------------------------------------------------------------------------------------------------------
;Initialize Timer2 modul. It generates 40ms Interrupt at 20Mhz Clock Frequency
Timer_1init:	mov		#0x0000, W0	;Continue in idle, Gating Disabled, 1:1, fosc/2
				mov		W0, T1CON
				mov		#0x061A, W0	;Period = 0005 (x256 = 61AA80 = d400 000 xTcy(100ns)= 40ms)				
				mov		W0, PR1
				clr		TMR1
				bset	IPC0, #13	;T1 Interrupt Priority = 0x04
				bclr	IFS0, #3	;Clear T1 Interrupt Flag
				bset	IEC0, #3	;Enable T1 Interrupt
				bset	T1CON, #15	;Timer1 ON
				clr		TRISD		;PORT.D output
				clr		LATD		;PORT.D = 0x0000
				return
;--------------------------------------------------------------------------------------------------------------
;Cyclic Display Refresh unit. Uses 0x0A00 - 0x0A9E GPR Adresses 80 word long space
RefreshDisplay:	mov		#0x0A00, W1		;DislpayRAM Start Addres
NextAddress:	mov		[W1++], W0		;Actual Adress -> W0	
				sl		W0, #8, W0		;High Byte Clearing
				swap	W0	
HD44780_Write:	mov		W0, LATD		;(1,3,5...) Originaly High Byte -> Databus
				bset	LATD, #10		;RS = 1		Character
				bclr	LATD, #9		;R/W = 0	Write
				bset	LATD, #8		;E = 1		Enable
				nop
				bclr	LATD, #8		;E = 1		Disable	
Delay_40us:		repeat	#0x0190			;400Tcy Pause 40us at 20Mhz
				nop				
TestLineEnd:	nop
TestEnd:		mov		#0x0AA0, W0		;[DisplayRAM End Address + (1 word)] -> W0
				cpseq	W0, W1			;W1 reched W0 (#0x0AA0)?
				goto	NextAddress		;Not reached, Continue whit next Display Address
				return					;FRISSÍTÉS VÉGE