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00006 #ifndef PICCOLO_14K50_H
00007 #define PICCOLO_14K50_H
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00020
00021 #if defined(PICCOLO_ALL) // Csak a főprogramhoz csatolhatjuk!
00022 #pragma config CPUDIV = NOCLKDIV // Nem osztjuk le az órajelet (48 MHz)
00023 #pragma config USBDIV = OFF // USB-hez nem osztjuk le az órajelet
00024 #pragma config FOSC = HS // HS oszcillátor (12 MHz)
00025 #pragma config PLLEN = ON // 4x PLL engedélyezés (4x12 = 48 MHz)
00026 #pragma config PCLKEN = ON // Elsődleges órajelgenerátor engedélyezve
00027 #pragma config FCMEN = OFF // Fail Safe Clock Monitor tiltása
00028 #pragma config IESO = OFF // Belső/külső oszcillátor átkapcsolás tiltása
00029 #pragma config PWRTEN = ON // Bekapcsoláskor 62 ms várakozás
00030 #pragma config BOREN = SBORDIS // Brown-out Reset hardveresen engedélyezve
00031 #pragma config BORV = 27 // Reset szint = 2,7 V
00032 #pragma config WDTEN = OFF // Watchdog timer letiltva
00033 #pragma config WDTPS = 256 // Watchdog utószámláló beállítása
00034 #pragma config MCLRE = OFF // MCLR (reset) bemenet letiltva, RA3 bemenet
00035 #pragma config HFOFST = ON // Rendszer óra nem vár HFINTOSC-ra
00036 #pragma config STVREN = ON // A verem túlcsordulása RESET-et okoz
00037 #pragma config LVP = OFF // Alacsonyfeszültségű programozás letiltva
00038 #pragma config XINST = OFF // Extended Instruction Set
00039 #if defined(HID_BOOTLOADER)
00040 #pragma config BBSIZ = ON // 4 kB boot blokk méret (HID bootloaderhez)
00041 #else
00042 #pragma config BBSIZ = OFF // 2 kB boot blokk méret (MCHPUSB bootloaderhez)
00043 #endif
00044 #pragma config CP0 = OFF // Kódvédelem kikapcsolva
00045 #pragma config CP1 = OFF
00046 #pragma config CPB = ON // Boot blokk kódvédelem bekapcsolva
00047 #pragma config WRT0 = OFF // Írásvédelem kikapcsolva
00048 #pragma config WRT1 = OFF
00049 #pragma config WRTB = ON // Boot Blokk írásvédelem bekapcsolva
00050 #pragma config WRTC = OFF // Konfigurációs blokk írható
00051 #pragma config EBTR0 = OFF // Táblázatolvasás ne legyen letiltva
00052 #pragma config EBTR1 = OFF
00053 #pragma config EBTRB = OFF
00054 #endif
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00061
00062 #define tris_self_power TRISAbits.TRISA2 // Input
00063 #if defined(USE_SELF_POWER_SENSE_IO)
00064 #define self_power PORTAbits.RA2
00065 #else
00066 #define self_power 1
00067 #endif
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00070
00071
00072
00073 #define tris_usb_bus_sense TRISAbits.TRISA1 // Input
00074 #if defined(USE_USB_BUS_SENSE_IO)
00075 #define USB_BUS_SENSE PORTAbits.RA1
00076 #else
00077 #define USB_BUS_SENSE 1
00078 #endif
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00080
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00082
00083
00084 #define CLOCK_FREQ 48000000
00085 #define LEDport LATC
00086 #define LEDtris TRISC
00087
00089 #define mInitAllLEDs() LATC &= 0xF0; TRISC &= 0xF0;
00090 #define mLED_1 LATCbits.LATC0
00091 #define mLED_2 LATCbits.LATC1
00092 #define mLED_3 LATCbits.LATC2
00093 #define mLED_4 LATCbits.LATC3
00094
00095 #define mGetLED_1() mLED_1
00096 #define mGetLED_2() mLED_2
00097 #define mGetLED_3() mLED_3
00098 #define mGetLED_4() mLED_4
00099
00100 #define mLED_1_On() mLED_1 = 1;
00101 #define mLED_2_On() mLED_2 = 1;
00102 #define mLED_3_On() mLED_3 = 1;
00103 #define mLED_4_On() mLED_4 = 1;
00104
00105 #define mLED_1_Off() mLED_1 = 0;
00106 #define mLED_2_Off() mLED_2 = 0;
00107 #define mLED_3_Off() mLED_3 = 0;
00108 #define mLED_4_Off() mLED_4 = 0;
00109
00110 #define mLED_1_Toggle() mLED_1 = !mLED_1;
00111 #define mLED_2_Toggle() mLED_2 = !mLED_2;
00112 #define mLED_3_Toggle() mLED_3 = !mLED_3;
00113 #define mLED_4_Toggle() mLED_4 = !mLED_4;
00114
00116 #define mInitSwitch1() // TRISAbits.TRISA3=1;
00117 #define SW1 PORTAbits.RA3
00118 #define sw2 PORTAbits.RA3 //Just for compatibility
00119
00121 #define INPUT_PIN 1
00122 #define OUTPUT_PIN 0
00123
00124 #define I2C_SDA TRISBbits.TRISB4
00125 #define I2C_SCL TRISBbits.TRISB6
00126
00127 #define SPI_SDI TRISBbits.TRISB4
00128 #define SPI_SCK TRISBbits.TRISB6
00129 #define SPI_SDO TRISCbits.TRISC7
00130 #define SPI_SS TRISCbits.TRISC6
00131
00133 #define ENABLE_RA3_PULLUP() WPUAbits.WPUA3 = 1
00134 #define DISABLE_RA3_PULLUP() WPUAbits.WPUA3 = 0
00135 #define ENABLE_RA4_PULLUP() WPUAbits.WPUA4 = 1
00136 #define DISABLE_RA4_PULLUP() WPUAbits.WPUA4 = 0
00137 #define ENABLE_RA5_PULLUP() WPUAbits.WPUA5 = 1
00138 #define DISABLE_RA5_PULLUP() WPUAbits.WPUA5 = 0
00139 #define ENABLE_RB4_PULLUP() WPUBbits.WPUB4 = 1
00140 #define DISABLE_RB4_PULLUP() WPUBbits.WPUB4 = 0
00141 #define ENABLE_RB5_PULLUP() WPUBbits.WPUB5 = 1
00142 #define DISABLE_RB5_PULLUP() WPUBbits.WPUB5 = 0
00143 #define ENABLE_RB6_PULLUP() WPUBbits.WPUB6 = 1
00144 #define DISABLE_RB6_PULLUP() WPUBbits.WPUB6 = 0
00145 #define ENABLE_RB7_PULLUP() WPUBbits.WPUB7 = 1
00146 #define DISABLE_RB7_PULLUP() WPUBbits.WPUB7 = 0
00147
00149 #define ENABLE_RA0_CN_INTERRUPT() IOCAbits.IOCA0 = 1
00150 #define DISABLE_RA0_CN_INTERRUPT() IOCAbits.IOCA0 = 0
00151 #define ENABLE_RA1_CN_INTERRUPT() IOCAbits.IOCA1 = 1
00152 #define DISABLE_RA1_CN_INTERRUPT() IOCAbits.IOCA1 = 0
00153 #define ENABLE_RA3_CN_INTERRUPT() IOCAbits.IOCA3 = 1
00154 #define DISABLE_RA3_CN_INTERRUPT() IOCAbits.IOCA3 = 0
00155 #define ENABLE_RA4_CN_INTERRUPT() IOCAbits.IOCA4 = 1
00156 #define DISABLE_RA4_CN_INTERRUPT() IOCAbits.IOCA4 = 0
00157 #define ENABLE_RA5_CN_INTERRUPT() IOCAbits.IOCA5 = 1
00158 #define DISABLE_RA5_CN_INTERRUPT() IOCAbits.IOCA5 = 0
00159 #define ENABLE_RB4_CN_INTERRUPT() IOCBbits.IOCB4 = 1
00160 #define DISABLE_RB4_CN_INTERRUPT() IOCBbits.IOCB4 = 0
00161 #define ENABLE_RB5_CN_INTERRUPT() IOCBbits.IOCB5 = 1
00162 #define DISABLE_RB5_CN_INTERRUPT() IOCBbits.IOCB5 = 0
00163 #define ENABLE_RB6_CN_INTERRUPT() IOCBbits.IOCB6 = 1
00164 #define DISABLE_RB6_CN_INTERRUPT() IOCBbits.IOCB6 = 0
00165 #define ENABLE_RB7_CN_INTERRUPT() IOCBbits.IOCB7 = 1
00166 #define DISABLE_RB7_CN_INTERRUPT() IOCBbits.IOCB7 = 0
00167
00169 #define DISABLE_ALL_ANALOG() {ANSEL=0; ANSELH=0x00; }
00170 #define ENABLE_ONE_ANALOG() {ANSEL=0; ANSELH=0x04; }
00171 #define ENABLE_TWO_ANALOG() {ANSEL=0; ANSELH=0x0C; }
00172 #define DISABLE_AN3_ANALOG() ANSELbits.ANS3=0
00173 #define ENABLE_AN3_ANALOG() ANSELbits.ANS3=1
00174 #define DISABLE_AN4_ANALOG() ANSELbits.ANS4=0
00175 #define ENABLE_AN4_ANALOG() ANSELbits.ANS4=1
00176 #define DISABLE_AN5_ANALOG() ANSELbits.ANS5=0
00177 #define ENABLE_AN5_ANALOG() ANSELbits.ANS5=1
00178 #define DISABLE_AN6_ANALOG() ANSELbits.ANS6=0
00179 #define ENABLE_AN6_ANALOG() ANSELbits.ANS6=1
00180 #define DISABLE_AN7_ANALOG() ANSELbits.ANS7=0
00181 #define ENABLE_AN7_ANALOG() ANSELbits.ANS7=1
00182 #define DISABLE_AN8_ANALOG() ANSELHbits.ANS8=0
00183 #define ENABLE_AN8_ANALOG() ANSELHbits.ANS8=1
00184 #define DISABLE_AN9_ANALOG() ANSELHbits.ANS9=0
00185 #define ENABLE_AN9_ANALOG() ANSELHbits.ANS9=1
00186 #define DISABLE_AN10_ANALOG() ANSELHbits.ANS10=0
00187 #define ENABLE_AN10_ANALOG() ANSELHbits.ANS10=1
00188 #define DISABLE_AN11_ANALOG() ANSELHbits.ANS11=0
00189 #define ENABLE_AN11_ANALOG() ANSELHbits.ANS11=1
00190
00192 #define CONFIG_AN3_AS_ANALOG() {TRISAbits.TRISA4=1; ANSELbits.ANS3=1; }
00193 #define CONFIG_AN4_AS_ANALOG() {TRISCbits.TRISC0=1; ANSELbits.ANS4=1; }
00194 #define CONFIG_AN5_AS_ANALOG() {TRISCbits.TRISC1=1; ANSELbits.ANS5=1; }
00195 #define CONFIG_AN6_AS_ANALOG() {TRISCbits.TRISC2=1; ANSELbits.ANS6=1; }
00196 #define CONFIG_AN7_AS_ANALOG() {TRISCbits.TRISC3=1; ANSELbits.ANS7=1; }
00197 #define CONFIG_AN8_AS_ANALOG() {TRISCbits.TRISC6=1; ANSELHbits.ANS8=1; }
00198 #define CONFIG_AN9_AS_ANALOG() {TRISCbits.TRISC7=1; ANSELHbits.ANS9=1; }
00199 #define CONFIG_AN10_AS_ANALOG() {TRISBbits.TRISB4=1; ANSELHbits.ANS10=1; }
00200 #define CONFIG_AN11_AS_ANALOG() {TRISBbits.TRISB5=1; ANSELHbits.ANS11=1; }
00201
00203 #define CONFIG_RA4_AS_DIGITAL_INPUT() {ANSELbits.ANS3=0; TRISAbits.TRISA4=1; }
00204 #define CONFIG_RA4_AS_DIGITAL_OUTPUT() {ANSELbits.ANS3=0; TRISAbits.TRISA4=0; }
00205 #define CONFIG_RA5_AS_DIGITAL_INPUT() TRISAbits.TRISA5=1
00206 #define CONFIG_RA5_AS_DIGITAL_OUTPUT() TRISAbits.TRISA5=0
00207 #define CONFIG_RB4_AS_DIGITAL_INPUT() {ANSELHbits.ANS10=0; TRISBbits.TRISB4=1; }
00208 #define CONFIG_RB4_AS_DIGITAL_OUTPUT() {ANSELHbits.ANS10=0; TRISBbits.TRISB4=0; }
00209 #define CONFIG_RB5_AS_DIGITAL_INPUT() {ANSELHbits.ANS11=0; TRISBbits.TRISB5=1; }
00210 #define CONFIG_RB5_AS_DIGITAL_OUTPUT() {ANSELHbits.ANS11=0; TRISBbits.TRISB5=0; }
00211 #define CONFIG_RB6_AS_DIGITAL_INPUT() TRISBbits.TRISB6=1
00212 #define CONFIG_RB6_AS_DIGITAL_OUTPUT() TRISBbits.TRISB6=0
00213 #define CONFIG_RB7_AS_DIGITAL_INPUT() TRISBbits.TRISB7=1
00214 #define CONFIG_RB7_AS_DIGITAL_OUTPUT() TRISBbits.TRISB7=0
00215 #define CONFIG_RC0_AS_DIGITAL_INPUT() {ANSELbits.ANS4=0; TRISCbits.TRISC0=1; }
00216 #define CONFIG_RC0_AS_DIGITAL_OUTPUT() {ANSELbits.ANS4=0; TRISCbits.TRISC0=0; }
00217 #define CONFIG_RC1_AS_DIGITAL_INPUT() {ANSELbits.ANS5=0; TRISCbits.TRISC1=1; }
00218 #define CONFIG_RC1_AS_DIGITAL_OUTPUT() {ANSELbits.ANS5=0; TRISCbits.TRISC1=0; }
00219 #define CONFIG_RC2_AS_DIGITAL_INPUT() {ANSELbits.ANS6=0; TRISCbits.TRISC2=1; }
00220 #define CONFIG_RC2_AS_DIGITAL_OUTPUT() {ANSELbits.ANS6=0; TRISCbits.TRISC2=0; }
00221 #define CONFIG_RC3_AS_DIGITAL_INPUT() {ANSELbits.ANS7=0; TRISCbits.TRISC3=1; }
00222 #define CONFIG_RC3_AS_DIGITAL_OUTPUT() {ANSELbits.ANS7=0; TRISCbits.TRISC3=0; }
00223 #define CONFIG_RC4_AS_DIGITAL_INPUT() TRISCbits.TRISC4=1
00224 #define CONFIG_RC4_AS_DIGITAL_OUTPUT() TRISCbits.TRISC4=0
00225 #define CONFIG_RC5_AS_DIGITAL_INPUT() TRISCbits.TRISC5=1
00226 #define CONFIG_RC5_AS_DIGITAL_OUTPUT() TRISCbits.TRISC5=0
00227 #define CONFIG_RC6_AS_DIGITAL_INPUT() {ANSELHbits.ANS8=0; TRISCbits.TRISC6=1; }
00228 #define CONFIG_RC6_AS_DIGITAL_OUTPUT() {ANSELHbits.ANS8=0; TRISCbits.TRISC6=0; }
00229 #define CONFIG_RC7_AS_DIGITAL_INPUT() {ANSELHbits.ANS9=0; TRISCbits.TRISC7=1; }
00230 #define CONFIG_RC7_AS_DIGITAL_OUTPUT() {ANSELHbits.ANS9=0; TRISCbits.TRISC7=0; }
00231
00233 #define mInitPOT() {TRISBbits.TRISB4=1;\
00234 ADCON0=0x29; ADCON1=0;\
00235 ADCON2=0x3E; ADCON2bits.ADFM = 1;}
00236
00238
00239 #define FVR_ENABLE 0b10000000 // FVR modul engedélyezve
00240 #define FVR_DISABLE 0b00000000 // FVR modul letiltva
00241 #define FVREN_MASK 0b01111111 // FVREN maszk
00242 #define FVR1S_1024 0b00010000 // FVR1S = 1,024 V
00243 #define FVR1S_2048 0b00100000 // FVR1S = 2,048 V
00244 #define FVR1S_4096 0b00110000 // FVR1S = 4,096 V
00245 #define FVR1S_MASK 0b11001111 // FVR1S maszk
00246 #define FVR_STATUS REFCON0bits.FVR1ST //0: ha FVR nem stabil
00247
00249
00250 #define DAC_ENABLE 0b10000000 // A programozható feszültségreferencia engedélyezése
00251 #define DAC_DISABLE 0b00000000 // A programozható feszültségreferencia letiltása
00252 #define D1EN_MASK 0b01111111 // A DAC engedélyező bit maszkja
00253 #define D1LPS_HI 0b01000000 // energiatakarékos módban a kimenet felhúzása
00254 #define D1LPS_LO 0b00000000 // energiatakarékos módban a kimenet lelhúzása
00255 #define D1LPS_MASK 0b10111111 // A D1LPS bit maszkja
00256 #define DACOUT_ENABLE 0b00100000 // A DAC kimenet kijut az RC2 lábra is
00257 #define DACOUT_DISABLE 0b00000000 // A DAC kimenet csak belül érhető el
00258 #define DAC1OE_MASK 0b11011111 // A DAC kimenet engedélyező bitjének maszkja
00259 #define D1PSS_VDD 0b00000000 // VDD a pozitív referencia
00260 #define D1PSS_VREF 0b00000100 // RC0/Vref+ a pozitív referencia
00261 #define D1PSS_FVR 0b00001000 // FVR a pozitív referencia
00262 #define D1PSS_MASK 0b11110011 // A pozitív referencia vezérlőbitjeinek maszkja
00263 #define D1NSS_VSS 0b00000000 // VSS a negatív referencia
00264 #define D1NSS_VREF 0b00000001 // RC1/Vref- a negatív referencia
00265 #define D1NSS_MASK 0b11111110 // A negatív referencia vezérlőbitjének maszkja
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00276 #define ENABLE_AN3 0x0008
00277 #define ENABLE_AN4 0x0010
00278 #define ENABLE_AN5 0x0020
00279 #define ENABLE_AN6 0x0040
00280 #define ENABLE_AN7 0x0080
00281 #define ENABLE_AN8 0x0100
00282 #define ENABLE_AN9 0x0200
00283 #define ENABLE_AN10 0x0400
00284 #define ENABLE_AN11 0x0800
00285
00286 #endif
00287