Makródefiníciók | |
#define | tris_self_power TRISAbits.TRISA2 |
#define | self_power 1 |
#define | tris_usb_bus_sense TRISAbits.TRISA1 |
#define | USB_BUS_SENSE 1 |
#define | CLOCK_FREQ 48000000 |
#define | LEDport LATC |
#define | LEDtris TRISC |
#define | mInitAllLEDs() LATC &= 0xF0; TRISC &= 0xF0; |
#define | mLED_1 LATCbits.LATC0 |
#define | mLED_2 LATCbits.LATC1 |
#define | mLED_3 LATCbits.LATC2 |
#define | mLED_4 LATCbits.LATC3 |
#define | mGetLED_1() mLED_1 |
#define | mGetLED_2() mLED_2 |
#define | mGetLED_3() mLED_3 |
#define | mGetLED_4() mLED_4 |
#define | mLED_1_On() mLED_1 = 1; |
#define | mLED_2_On() mLED_2 = 1; |
#define | mLED_3_On() mLED_3 = 1; |
#define | mLED_4_On() mLED_4 = 1; |
#define | mLED_1_Off() mLED_1 = 0; |
#define | mLED_2_Off() mLED_2 = 0; |
#define | mLED_3_Off() mLED_3 = 0; |
#define | mLED_4_Off() mLED_4 = 0; |
#define | mLED_1_Toggle() mLED_1 = !mLED_1; |
#define | mLED_2_Toggle() mLED_2 = !mLED_2; |
#define | mLED_3_Toggle() mLED_3 = !mLED_3; |
#define | mLED_4_Toggle() mLED_4 = !mLED_4; |
#define | mInitSwitch1() |
#define | SW1 PORTAbits.RA3 |
#define | sw2 PORTAbits.RA3 |
#define | INPUT_PIN 1 |
#define | OUTPUT_PIN 0 |
#define | I2C_SDA TRISBbits.TRISB4 |
#define | I2C_SCL TRISBbits.TRISB6 |
#define | SPI_SDI TRISBbits.TRISB4 |
#define | SPI_SCK TRISBbits.TRISB6 |
#define | SPI_SDO TRISCbits.TRISC7 |
#define | SPI_SS TRISCbits.TRISC6 |
#define | ENABLE_RA3_PULLUP() WPUAbits.WPUA3 = 1 |
#define | DISABLE_RA3_PULLUP() WPUAbits.WPUA3 = 0 |
#define | ENABLE_RA4_PULLUP() WPUAbits.WPUA4 = 1 |
#define | DISABLE_RA4_PULLUP() WPUAbits.WPUA4 = 0 |
#define | ENABLE_RA5_PULLUP() WPUAbits.WPUA5 = 1 |
#define | DISABLE_RA5_PULLUP() WPUAbits.WPUA5 = 0 |
#define | ENABLE_RB4_PULLUP() WPUBbits.WPUB4 = 1 |
#define | DISABLE_RB4_PULLUP() WPUBbits.WPUB4 = 0 |
#define | ENABLE_RB5_PULLUP() WPUBbits.WPUB5 = 1 |
#define | DISABLE_RB5_PULLUP() WPUBbits.WPUB5 = 0 |
#define | ENABLE_RB6_PULLUP() WPUBbits.WPUB6 = 1 |
#define | DISABLE_RB6_PULLUP() WPUBbits.WPUB6 = 0 |
#define | ENABLE_RB7_PULLUP() WPUBbits.WPUB7 = 1 |
#define | DISABLE_RB7_PULLUP() WPUBbits.WPUB7 = 0 |
#define | ENABLE_RA0_CN_INTERRUPT() IOCAbits.IOCA0 = 1 |
#define | DISABLE_RA0_CN_INTERRUPT() IOCAbits.IOCA0 = 0 |
#define | ENABLE_RA1_CN_INTERRUPT() IOCAbits.IOCA1 = 1 |
#define | DISABLE_RA1_CN_INTERRUPT() IOCAbits.IOCA1 = 0 |
#define | ENABLE_RA3_CN_INTERRUPT() IOCAbits.IOCA3 = 1 |
#define | DISABLE_RA3_CN_INTERRUPT() IOCAbits.IOCA3 = 0 |
#define | ENABLE_RA4_CN_INTERRUPT() IOCAbits.IOCA4 = 1 |
#define | DISABLE_RA4_CN_INTERRUPT() IOCAbits.IOCA4 = 0 |
#define | ENABLE_RA5_CN_INTERRUPT() IOCAbits.IOCA5 = 1 |
#define | DISABLE_RA5_CN_INTERRUPT() IOCAbits.IOCA5 = 0 |
#define | ENABLE_RB4_CN_INTERRUPT() IOCBbits.IOCB4 = 1 |
#define | DISABLE_RB4_CN_INTERRUPT() IOCBbits.IOCB4 = 0 |
#define | ENABLE_RB5_CN_INTERRUPT() IOCBbits.IOCB5 = 1 |
#define | DISABLE_RB5_CN_INTERRUPT() IOCBbits.IOCB5 = 0 |
#define | ENABLE_RB6_CN_INTERRUPT() IOCBbits.IOCB6 = 1 |
#define | DISABLE_RB6_CN_INTERRUPT() IOCBbits.IOCB6 = 0 |
#define | ENABLE_RB7_CN_INTERRUPT() IOCBbits.IOCB7 = 1 |
#define | DISABLE_RB7_CN_INTERRUPT() IOCBbits.IOCB7 = 0 |
#define | DISABLE_ALL_ANALOG() {ANSEL=0; ANSELH=0x00; } |
#define | ENABLE_ONE_ANALOG() {ANSEL=0; ANSELH=0x04; } |
#define | ENABLE_TWO_ANALOG() {ANSEL=0; ANSELH=0x0C; } |
#define | DISABLE_AN3_ANALOG() ANSELbits.ANS3=0 |
#define | ENABLE_AN3_ANALOG() ANSELbits.ANS3=1 |
#define | DISABLE_AN4_ANALOG() ANSELbits.ANS4=0 |
#define | ENABLE_AN4_ANALOG() ANSELbits.ANS4=1 |
#define | DISABLE_AN5_ANALOG() ANSELbits.ANS5=0 |
#define | ENABLE_AN5_ANALOG() ANSELbits.ANS5=1 |
#define | DISABLE_AN6_ANALOG() ANSELbits.ANS6=0 |
#define | ENABLE_AN6_ANALOG() ANSELbits.ANS6=1 |
#define | DISABLE_AN7_ANALOG() ANSELbits.ANS7=0 |
#define | ENABLE_AN7_ANALOG() ANSELbits.ANS7=1 |
#define | DISABLE_AN8_ANALOG() ANSELHbits.ANS8=0 |
#define | ENABLE_AN8_ANALOG() ANSELHbits.ANS8=1 |
#define | DISABLE_AN9_ANALOG() ANSELHbits.ANS9=0 |
#define | ENABLE_AN9_ANALOG() ANSELHbits.ANS9=1 |
#define | DISABLE_AN10_ANALOG() ANSELHbits.ANS10=0 |
#define | ENABLE_AN10_ANALOG() ANSELHbits.ANS10=1 |
#define | DISABLE_AN11_ANALOG() ANSELHbits.ANS11=0 |
#define | ENABLE_AN11_ANALOG() ANSELHbits.ANS11=1 |
#define | CONFIG_AN3_AS_ANALOG() {TRISAbits.TRISA4=1; ANSELbits.ANS3=1; } |
#define | CONFIG_AN4_AS_ANALOG() {TRISCbits.TRISC0=1; ANSELbits.ANS4=1; } |
#define | CONFIG_AN5_AS_ANALOG() {TRISCbits.TRISC1=1; ANSELbits.ANS5=1; } |
#define | CONFIG_AN6_AS_ANALOG() {TRISCbits.TRISC2=1; ANSELbits.ANS6=1; } |
#define | CONFIG_AN7_AS_ANALOG() {TRISCbits.TRISC3=1; ANSELbits.ANS7=1; } |
#define | CONFIG_AN8_AS_ANALOG() {TRISCbits.TRISC6=1; ANSELHbits.ANS8=1; } |
#define | CONFIG_AN9_AS_ANALOG() {TRISCbits.TRISC7=1; ANSELHbits.ANS9=1; } |
#define | CONFIG_AN10_AS_ANALOG() {TRISBbits.TRISB4=1; ANSELHbits.ANS10=1; } |
#define | CONFIG_AN11_AS_ANALOG() {TRISBbits.TRISB5=1; ANSELHbits.ANS11=1; } |
#define | CONFIG_RA4_AS_DIGITAL_INPUT() {ANSELbits.ANS3=0; TRISAbits.TRISA4=1; } |
#define | CONFIG_RA4_AS_DIGITAL_OUTPUT() {ANSELbits.ANS3=0; TRISAbits.TRISA4=0; } |
#define | CONFIG_RA5_AS_DIGITAL_INPUT() TRISAbits.TRISA5=1 |
#define | CONFIG_RA5_AS_DIGITAL_OUTPUT() TRISAbits.TRISA5=0 |
#define | CONFIG_RB4_AS_DIGITAL_INPUT() {ANSELHbits.ANS10=0; TRISBbits.TRISB4=1; } |
#define | CONFIG_RB4_AS_DIGITAL_OUTPUT() {ANSELHbits.ANS10=0; TRISBbits.TRISB4=0; } |
#define | CONFIG_RB5_AS_DIGITAL_INPUT() {ANSELHbits.ANS11=0; TRISBbits.TRISB5=1; } |
#define | CONFIG_RB5_AS_DIGITAL_OUTPUT() {ANSELHbits.ANS11=0; TRISBbits.TRISB5=0; } |
#define | CONFIG_RB6_AS_DIGITAL_INPUT() TRISBbits.TRISB6=1 |
#define | CONFIG_RB6_AS_DIGITAL_OUTPUT() TRISBbits.TRISB6=0 |
#define | CONFIG_RB7_AS_DIGITAL_INPUT() TRISBbits.TRISB7=1 |
#define | CONFIG_RB7_AS_DIGITAL_OUTPUT() TRISBbits.TRISB7=0 |
#define | CONFIG_RC0_AS_DIGITAL_INPUT() {ANSELbits.ANS4=0; TRISCbits.TRISC0=1; } |
#define | CONFIG_RC0_AS_DIGITAL_OUTPUT() {ANSELbits.ANS4=0; TRISCbits.TRISC0=0; } |
#define | CONFIG_RC1_AS_DIGITAL_INPUT() {ANSELbits.ANS5=0; TRISCbits.TRISC1=1; } |
#define | CONFIG_RC1_AS_DIGITAL_OUTPUT() {ANSELbits.ANS5=0; TRISCbits.TRISC1=0; } |
#define | CONFIG_RC2_AS_DIGITAL_INPUT() {ANSELbits.ANS6=0; TRISCbits.TRISC2=1; } |
#define | CONFIG_RC2_AS_DIGITAL_OUTPUT() {ANSELbits.ANS6=0; TRISCbits.TRISC2=0; } |
#define | CONFIG_RC3_AS_DIGITAL_INPUT() {ANSELbits.ANS7=0; TRISCbits.TRISC3=1; } |
#define | CONFIG_RC3_AS_DIGITAL_OUTPUT() {ANSELbits.ANS7=0; TRISCbits.TRISC3=0; } |
#define | CONFIG_RC4_AS_DIGITAL_INPUT() TRISCbits.TRISC4=1 |
#define | CONFIG_RC4_AS_DIGITAL_OUTPUT() TRISCbits.TRISC4=0 |
#define | CONFIG_RC5_AS_DIGITAL_INPUT() TRISCbits.TRISC5=1 |
#define | CONFIG_RC5_AS_DIGITAL_OUTPUT() TRISCbits.TRISC5=0 |
#define | CONFIG_RC6_AS_DIGITAL_INPUT() {ANSELHbits.ANS8=0; TRISCbits.TRISC6=1; } |
#define | CONFIG_RC6_AS_DIGITAL_OUTPUT() {ANSELHbits.ANS8=0; TRISCbits.TRISC6=0; } |
#define | CONFIG_RC7_AS_DIGITAL_INPUT() {ANSELHbits.ANS9=0; TRISCbits.TRISC7=1; } |
#define | CONFIG_RC7_AS_DIGITAL_OUTPUT() {ANSELHbits.ANS9=0; TRISCbits.TRISC7=0; } |
#define | mInitPOT() |
#define | FVR_ENABLE 0b10000000 |
#define | FVR_DISABLE 0b00000000 |
#define | FVREN_MASK 0b01111111 |
#define | FVR1S_1024 0b00010000 |
#define | FVR1S_2048 0b00100000 |
#define | FVR1S_4096 0b00110000 |
#define | FVR1S_MASK 0b11001111 |
#define | FVR_STATUS REFCON0bits.FVR1ST |
#define | DAC_ENABLE 0b10000000 |
#define | DAC_DISABLE 0b00000000 |
#define | D1EN_MASK 0b01111111 |
#define | D1LPS_HI 0b01000000 |
#define | D1LPS_LO 0b00000000 |
#define | D1LPS_MASK 0b10111111 |
#define | DACOUT_ENABLE 0b00100000 |
#define | DACOUT_DISABLE 0b00000000 |
#define | DAC1OE_MASK 0b11011111 |
#define | D1PSS_VDD 0b00000000 |
#define | D1PSS_VREF 0b00000100 |
#define | D1PSS_FVR 0b00001000 |
#define | D1PSS_MASK 0b11110011 |
#define | D1NSS_VSS 0b00000000 |
#define | D1NSS_VREF 0b00000001 |
#define | D1NSS_MASK 0b11111110 |
#define | ENABLE_AN3 0x0008 |
#define | ENABLE_AN4 0x0010 |
#define | ENABLE_AN5 0x0020 |
#define | ENABLE_AN6 0x0040 |
#define | ENABLE_AN7 0x0080 |
#define | ENABLE_AN8 0x0100 |
#define | ENABLE_AN9 0x0200 |
#define | ENABLE_AN10 0x0400 |
#define | ENABLE_AN11 0x0800 |
Definíció a(z) piccolo-14k50.h fájlban.
#define CONFIG_AN3_AS_ANALOG | ( | ) | {TRISAbits.TRISA4=1; ANSELbits.ANS3=1; } |
ANALÓG BEMENETEK KONFIGURÁLÁSA
Definíció a(z) piccolo-14k50.h fájl 192. sorában.
#define CONFIG_RA4_AS_DIGITAL_INPUT | ( | ) | {ANSELbits.ANS3=0; TRISAbits.TRISA4=1; } |
DIGITÁLIS KI/BEMENETEK KONFIGURÁLÁSA
Definíció a(z) piccolo-14k50.h fájl 203. sorában.
#define DAC_ENABLE 0b10000000 |
Változtatható feszültségű referencia (DAC)
Definíció a(z) piccolo-14k50.h fájl 250. sorában.
#define DISABLE_ALL_ANALOG | ( | ) | {ANSEL=0; ANSELH=0x00; } |
ANALÓG BEMENETEK ENGEDÉLYEZÉSE/TILTÁSA
Definíció a(z) piccolo-14k50.h fájl 169. sorában.
#define ENABLE_RA0_CN_INTERRUPT | ( | ) | IOCAbits.IOCA0 = 1 |
VÁLTOZÁSJELZŐ INTERRUPTOK ENGEDÉLYEZÉSE/TILTÁSA
Definíció a(z) piccolo-14k50.h fájl 149. sorában.
#define ENABLE_RA3_PULLUP | ( | ) | WPUAbits.WPUA3 = 1 |
BELSŐ FELHÚZÁSOK ENGEDÉLYEZÉSE/TILTÁSA
Definíció a(z) piccolo-14k50.h fájl 133. sorában.
#define FVR_ENABLE 0b10000000 |
Fix feszültségű referencia (FVR)
Definíció a(z) piccolo-14k50.h fájl 239. sorában.
#define INPUT_PIN 1 |
I/O pin definitions
Definíció a(z) piccolo-14k50.h fájl 121. sorában.
#define mInitAllLEDs | ( | ) | LATC &= 0xF0; TRISC &= 0xF0; |
LED-ek
Definíció a(z) piccolo-14k50.h fájl 89. sorában.
#define mInitPOT | ( | ) |
Érték:
{TRISBbits.TRISB4=1;\ ADCON0=0x29; ADCON1=0;\ ADCON2=0x3E; ADCON2bits.ADFM = 1;}
Definíció a(z) piccolo-14k50.h fájl 233. sorában.
#define mInitSwitch1 | ( | ) |
SWITCH
Definíció a(z) piccolo-14k50.h fájl 116. sorában.