library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Quartz 50MHz
entity gen_1hz is
    Port ( clk : in  STD_LOGIC;
           one_hz : out  STD_LOGIC);
end gen_1hz;
architecture Behavioral of gen_1hz is
signal cnt:integer range 0 to 50000000;
signal sig_one_hz:std_logic:='0';
begin
process(clk)
  begin
  if(rising_edge(clk))then
    cnt<=cnt+1;
    if(cnt=50000000)then
      cnt<=0;
      sig_one_hz<=not sig_one_hz;
    end if;
  end if;
end process;
one_hz<=sig_one_hz;
end Behavioral;