cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: CPLDLED Date: 5-23-2021, 2:53PM
Device Used: XC9536XL-5-VQ44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
31 /36 ( 86%) 61 /180 ( 34%) 34 /108 ( 31%) 28 /36 ( 78%) 4 /34 ( 12%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 21/54 37/90 4/17
FB2 13/18 13/54 24/90 0/17
----- ----- ----- -----
31/36 34/108 61/180 4/34
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 1 1 | I/O : 2 28
Output : 3 3 | GCK/IO : 2 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 4 4
** Power Data **
There are 31 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'CPLDLED.ise'.
************************* Summary of Mapped Logic ************************
** 3 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
OUTLED2 2 3 FB1_3 43~ GCK/I/O O STD FAST
OUTLED3 3 4 FB1_4 42~ I/O O STD FAST
OUTLED1 3 4 FB1_5 44~ GCK/I/O O STD FAST
** 28 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
XLXN_39 1 1 FB1_1 STD RESET
XLXN_6<15> 2 16 FB1_2 STD RESET
XLXN_42 2 4 FB1_6 STD RESET
XLXN_41 2 3 FB1_7 STD RESET
XLXN_40 2 2 FB1_8 STD RESET
XLXI_3/Q<9> 2 10 FB1_9 STD RESET
XLXI_3/Q<8> 2 9 FB1_10 STD RESET
XLXI_3/Q<7> 2 8 FB1_11 STD RESET
XLXI_3/Q<6> 2 7 FB1_12 STD RESET
XLXI_3/Q<5> 2 6 FB1_13 STD RESET
XLXI_3/Q<14> 2 15 FB1_14 STD RESET
XLXI_3/Q<13> 2 14 FB1_15 STD RESET
XLXI_3/Q<12> 2 13 FB1_16 STD RESET
XLXI_3/Q<11> 2 12 FB1_17 STD RESET
XLXI_3/Q<10> 2 11 FB1_18 STD RESET
XLXI_3/Q<0> 1 1 FB2_6 STD RESET
XLXI_19/Q<0> 1 1 FB2_7 STD RESET
XLXN_26<7> 2 8 FB2_8 STD RESET
XLXI_3/Q<4> 2 5 FB2_9 STD RESET
XLXI_3/Q<3> 2 4 FB2_10 STD RESET
XLXI_3/Q<2> 2 3 FB2_11 STD RESET
XLXI_3/Q<1> 2 2 FB2_12 STD RESET
XLXI_19/Q<6> 2 7 FB2_13 STD RESET
XLXI_19/Q<5> 2 6 FB2_14 STD RESET
XLXI_19/Q<4> 2 5 FB2_15 STD RESET
XLXI_19/Q<3> 2 4 FB2_16 STD RESET
XLXI_19/Q<2> 2 3 FB2_17 STD RESET
XLXI_19/Q<1> 2 2 FB2_18 STD RESET
** 1 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
CLK FB1_9 5~ I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 21/33
Number of signals used by logic mapping into function block: 21
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
XLXN_39 1 0 0 4 FB1_1 40 I/O (b)
XLXN_6<15> 2 0 0 3 FB1_2 41 I/O (b)
OUTLED2 2 0 0 3 FB1_3 43~ GCK/I/O O
OUTLED3 3 0 0 2 FB1_4 42~ I/O O
OUTLED1 3 0 0 2 FB1_5 44~ GCK/I/O O
XLXN_42 2 0 0 3 FB1_6 2 I/O (b)
XLXN_41 2 0 0 3 FB1_7 1 GCK/I/O (b)
XLXN_40 2 0 0 3 FB1_8 3 I/O (b)
XLXI_3/Q<9> 2 0 0 3 FB1_9 5 I/O I
XLXI_3/Q<8> 2 0 0 3 FB1_10 6 I/O (b)
XLXI_3/Q<7> 2 0 0 3 FB1_11 7 I/O (b)
XLXI_3/Q<6> 2 0 0 3 FB1_12 8 I/O (b)
XLXI_3/Q<5> 2 0 0 3 FB1_13 12 I/O (b)
XLXI_3/Q<14> 2 0 0 3 FB1_14 13 I/O (b)
XLXI_3/Q<13> 2 0 0 3 FB1_15 14 I/O (b)
XLXI_3/Q<12> 2 0 0 3 FB1_16 16 I/O (b)
XLXI_3/Q<11> 2 0 0 3 FB1_17 18 I/O (b)
XLXI_3/Q<10> 2 0 0 3 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: CLK 8: XLXI_3/Q<1> 15: XLXI_3/Q<8>
2: XLXI_3/Q<0> 9: XLXI_3/Q<2> 16: XLXI_3/Q<9>
3: XLXI_3/Q<10> 10: XLXI_3/Q<3> 17: XLXN_26<7>
4: XLXI_3/Q<11> 11: XLXI_3/Q<4> 18: XLXN_39
5: XLXI_3/Q<12> 12: XLXI_3/Q<5> 19: XLXN_40
6: XLXI_3/Q<13> 13: XLXI_3/Q<6> 20: XLXN_41
7: XLXI_3/Q<14> 14: XLXI_3/Q<7> 21: XLXN_42
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
XLXN_39 ................X....................... 1
XLXN_6<15> XXXXXXXXXXXXXXXX........................ 16
OUTLED2 .................XXX.................... 3
OUTLED3 .................XXXX................... 4
OUTLED1 .................XXXX................... 4
XLXN_42 ................XXXX.................... 4
XLXN_41 ................XXX..................... 3
XLXN_40 ................XX...................... 2
XLXI_3/Q<9> XX.....XXXXXXXX......................... 10
XLXI_3/Q<8> XX.....XXXXXXX.......................... 9
XLXI_3/Q<7> XX.....XXXXXX........................... 8
XLXI_3/Q<6> XX.....XXXXX............................ 7
XLXI_3/Q<5> XX.....XXXX............................. 6
XLXI_3/Q<14> XXXXXX.XXXXXXXXX........................ 15
XLXI_3/Q<13> XXXXX..XXXXXXXXX........................ 14
XLXI_3/Q<12> XXXX...XXXXXXXXX........................ 13
XLXI_3/Q<11> XXX....XXXXXXXXX........................ 12
XLXI_3/Q<10> XX.....XXXXXXXXX........................ 11
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 13/41
Number of signals used by logic mapping into function block: 13
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 39 I/O
(unused) 0 0 0 5 FB2_2 38 I/O
(unused) 0 0 0 5 FB2_3 36 GTS/I/O
(unused) 0 0 0 5 FB2_4 37 I/O
(unused) 0 0 0 5 FB2_5 34 GTS/I/O
XLXI_3/Q<0> 1 0 0 4 FB2_6 33 GSR/I/O (b)
XLXI_19/Q<0> 1 0 0 4 FB2_7 32 I/O (b)
XLXN_26<7> 2 0 0 3 FB2_8 31 I/O (b)
XLXI_3/Q<4> 2 0 0 3 FB2_9 30 I/O (b)
XLXI_3/Q<3> 2 0 0 3 FB2_10 29 I/O (b)
XLXI_3/Q<2> 2 0 0 3 FB2_11 28 I/O (b)
XLXI_3/Q<1> 2 0 0 3 FB2_12 27 I/O (b)
XLXI_19/Q<6> 2 0 0 3 FB2_13 23 I/O (b)
XLXI_19/Q<5> 2 0 0 3 FB2_14 22 I/O (b)
XLXI_19/Q<4> 2 0 0 3 FB2_15 21 I/O (b)
XLXI_19/Q<3> 2 0 0 3 FB2_16 20 I/O (b)
XLXI_19/Q<2> 2 0 0 3 FB2_17 19 I/O (b)
XLXI_19/Q<1> 2 0 0 3 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: CLK 6: XLXI_19/Q<4> 10: XLXI_3/Q<1>
2: XLXI_19/Q<0> 7: XLXI_19/Q<5> 11: XLXI_3/Q<2>
3: XLXI_19/Q<1> 8: XLXI_19/Q<6> 12: XLXI_3/Q<3>
4: XLXI_19/Q<2> 9: XLXI_3/Q<0> 13: XLXN_6<15>
5: XLXI_19/Q<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
XLXI_3/Q<0> X....................................... 1
XLXI_19/Q<0> ............X........................... 1
XLXN_26<7> .XXXXXXX....X........................... 8
XLXI_3/Q<4> X.......XXXX............................ 5
XLXI_3/Q<3> X.......XXX............................. 4
XLXI_3/Q<2> X.......XX.............................. 3
XLXI_3/Q<1> X.......X............................... 2
XLXI_19/Q<6> .XXXXXX.....X........................... 7
XLXI_19/Q<5> .XXXXX......X........................... 6
XLXI_19/Q<4> .XXXX.......X........................... 5
XLXI_19/Q<3> .XXX........X........................... 4
XLXI_19/Q<2> .XX.........X........................... 3
XLXI_19/Q<1> .X..........X........................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
OUTLED1 <= ((XLXN_41 AND XLXN_42)
OR (NOT XLXN_39 AND NOT XLXN_41 AND NOT XLXN_42)
OR (NOT XLXN_40 AND NOT XLXN_41 AND NOT XLXN_42));
OUTLED2 <= ((XLXN_40 AND NOT XLXN_41)
OR (NOT XLXN_39 AND NOT XLXN_40 AND XLXN_41));
OUTLED3 <= ((XLXN_41 AND NOT XLXN_42)
OR (NOT XLXN_39 AND NOT XLXN_41 AND XLXN_42)
OR (NOT XLXN_40 AND NOT XLXN_41 AND XLXN_42));
FTCPE_XLXI_19/Q0: FTCPE port map (XLXI_19/Q(0),'1',XLXN_6(15),'0','0');
FTCPE_XLXI_19/Q1: FTCPE port map (XLXI_19/Q(1),XLXI_19/Q(0),XLXN_6(15),'0','0');
FTCPE_XLXI_19/Q2: FTCPE port map (XLXI_19/Q(2),XLXI_19/Q_T(2),XLXN_6(15),'0','0');
XLXI_19/Q_T(2) <= (XLXI_19/Q(0) AND XLXI_19/Q(1));
FTCPE_XLXI_19/Q3: FTCPE port map (XLXI_19/Q(3),XLXI_19/Q_T(3),XLXN_6(15),'0','0');
XLXI_19/Q_T(3) <= (XLXI_19/Q(0) AND XLXI_19/Q(1) AND XLXI_19/Q(2));
FTCPE_XLXI_19/Q4: FTCPE port map (XLXI_19/Q(4),XLXI_19/Q_T(4),XLXN_6(15),'0','0');
XLXI_19/Q_T(4) <= (XLXI_19/Q(0) AND XLXI_19/Q(1) AND XLXI_19/Q(2) AND
XLXI_19/Q(3));
FTCPE_XLXI_19/Q5: FTCPE port map (XLXI_19/Q(5),XLXI_19/Q_T(5),XLXN_6(15),'0','0');
XLXI_19/Q_T(5) <= (XLXI_19/Q(0) AND XLXI_19/Q(1) AND XLXI_19/Q(4) AND
XLXI_19/Q(2) AND XLXI_19/Q(3));
FTCPE_XLXI_19/Q6: FTCPE port map (XLXI_19/Q(6),XLXI_19/Q_T(6),XLXN_6(15),'0','0');
XLXI_19/Q_T(6) <= (XLXI_19/Q(0) AND XLXI_19/Q(1) AND XLXI_19/Q(4) AND
XLXI_19/Q(2) AND XLXI_19/Q(5) AND XLXI_19/Q(3));
FTCPE_XLXI_3/Q0: FTCPE port map (XLXI_3/Q(0),'1',CLK,'0','0');
FTCPE_XLXI_3/Q1: FTCPE port map (XLXI_3/Q(1),XLXI_3/Q(0),CLK,'0','0');
FTCPE_XLXI_3/Q2: FTCPE port map (XLXI_3/Q(2),XLXI_3/Q_T(2),CLK,'0','0');
XLXI_3/Q_T(2) <= (XLXI_3/Q(0) AND XLXI_3/Q(1));
FTCPE_XLXI_3/Q3: FTCPE port map (XLXI_3/Q(3),XLXI_3/Q_T(3),CLK,'0','0');
XLXI_3/Q_T(3) <= (XLXI_3/Q(0) AND XLXI_3/Q(1) AND XLXI_3/Q(2));
FTCPE_XLXI_3/Q4: FTCPE port map (XLXI_3/Q(4),XLXI_3/Q_T(4),CLK,'0','0');
XLXI_3/Q_T(4) <= (XLXI_3/Q(0) AND XLXI_3/Q(1) AND XLXI_3/Q(2) AND
XLXI_3/Q(3));
FTCPE_XLXI_3/Q5: FTCPE port map (XLXI_3/Q(5),XLXI_3/Q_T(5),CLK,'0','0');
XLXI_3/Q_T(5) <= (XLXI_3/Q(0) AND XLXI_3/Q(4) AND XLXI_3/Q(1) AND
XLXI_3/Q(2) AND XLXI_3/Q(3));
FTCPE_XLXI_3/Q6: FTCPE port map (XLXI_3/Q(6),XLXI_3/Q_T(6),CLK,'0','0');
XLXI_3/Q_T(6) <= (XLXI_3/Q(0) AND XLXI_3/Q(4) AND XLXI_3/Q(1) AND
XLXI_3/Q(5) AND XLXI_3/Q(2) AND XLXI_3/Q(3));
FTCPE_XLXI_3/Q7: FTCPE port map (XLXI_3/Q(7),XLXI_3/Q_T(7),CLK,'0','0');
XLXI_3/Q_T(7) <= (XLXI_3/Q(0) AND XLXI_3/Q(4) AND XLXI_3/Q(1) AND
XLXI_3/Q(5) AND XLXI_3/Q(2) AND XLXI_3/Q(6) AND XLXI_3/Q(3));
FTCPE_XLXI_3/Q8: FTCPE port map (XLXI_3/Q(8),XLXI_3/Q_T(8),CLK,'0','0');
XLXI_3/Q_T(8) <= (XLXI_3/Q(0) AND XLXI_3/Q(4) AND XLXI_3/Q(1) AND
XLXI_3/Q(5) AND XLXI_3/Q(2) AND XLXI_3/Q(6) AND XLXI_3/Q(3) AND
XLXI_3/Q(7));
FTCPE_XLXI_3/Q9: FTCPE port map (XLXI_3/Q(9),XLXI_3/Q_T(9),CLK,'0','0');
XLXI_3/Q_T(9) <= (XLXI_3/Q(0) AND XLXI_3/Q(4) AND XLXI_3/Q(8) AND
XLXI_3/Q(1) AND XLXI_3/Q(5) AND XLXI_3/Q(2) AND XLXI_3/Q(6) AND
XLXI_3/Q(3) AND XLXI_3/Q(7));
FTCPE_XLXI_3/Q10: FTCPE port map (XLXI_3/Q(10),XLXI_3/Q_T(10),CLK,'0','0');
XLXI_3/Q_T(10) <= (XLXI_3/Q(0) AND XLXI_3/Q(4) AND XLXI_3/Q(8) AND
XLXI_3/Q(1) AND XLXI_3/Q(5) AND XLXI_3/Q(9) AND XLXI_3/Q(2) AND
XLXI_3/Q(6) AND XLXI_3/Q(3) AND XLXI_3/Q(7));
FTCPE_XLXI_3/Q11: FTCPE port map (XLXI_3/Q(11),XLXI_3/Q_T(11),CLK,'0','0');
XLXI_3/Q_T(11) <= (XLXI_3/Q(0) AND XLXI_3/Q(4) AND XLXI_3/Q(8) AND
XLXI_3/Q(1) AND XLXI_3/Q(5) AND XLXI_3/Q(9) AND XLXI_3/Q(10) AND
XLXI_3/Q(2) AND XLXI_3/Q(6) AND XLXI_3/Q(3) AND XLXI_3/Q(7));
FTCPE_XLXI_3/Q12: FTCPE port map (XLXI_3/Q(12),XLXI_3/Q_T(12),CLK,'0','0');
XLXI_3/Q_T(12) <= (XLXI_3/Q(0) AND XLXI_3/Q(4) AND XLXI_3/Q(8) AND
XLXI_3/Q(1) AND XLXI_3/Q(5) AND XLXI_3/Q(9) AND XLXI_3/Q(10) AND
XLXI_3/Q(2) AND XLXI_3/Q(6) AND XLXI_3/Q(11) AND XLXI_3/Q(3) AND
XLXI_3/Q(7));
FTCPE_XLXI_3/Q13: FTCPE port map (XLXI_3/Q(13),XLXI_3/Q_T(13),CLK,'0','0');
XLXI_3/Q_T(13) <= (XLXI_3/Q(0) AND XLXI_3/Q(4) AND XLXI_3/Q(8) AND
XLXI_3/Q(12) AND XLXI_3/Q(1) AND XLXI_3/Q(5) AND XLXI_3/Q(9) AND
XLXI_3/Q(10) AND XLXI_3/Q(2) AND XLXI_3/Q(6) AND XLXI_3/Q(11) AND
XLXI_3/Q(3) AND XLXI_3/Q(7));
FTCPE_XLXI_3/Q14: FTCPE port map (XLXI_3/Q(14),XLXI_3/Q_T(14),CLK,'0','0');
XLXI_3/Q_T(14) <= (XLXI_3/Q(0) AND XLXI_3/Q(4) AND XLXI_3/Q(8) AND
XLXI_3/Q(12) AND XLXI_3/Q(1) AND XLXI_3/Q(5) AND XLXI_3/Q(9) AND
XLXI_3/Q(10) AND XLXI_3/Q(13) AND XLXI_3/Q(2) AND XLXI_3/Q(6) AND
XLXI_3/Q(11) AND XLXI_3/Q(3) AND XLXI_3/Q(7));
FTCPE_XLXN_267: FTCPE port map (XLXN_26(7),XLXN_26_T(7),XLXN_6(15),'0','0');
XLXN_26_T(7) <= (XLXI_19/Q(0) AND XLXI_19/Q(1) AND XLXI_19/Q(4) AND
XLXI_19/Q(2) AND XLXI_19/Q(5) AND XLXI_19/Q(3) AND XLXI_19/Q(6));
FTCPE_XLXN_39: FTCPE port map (XLXN_39,'1',XLXN_26(7),'0','0');
FTCPE_XLXN_40: FTCPE port map (XLXN_40,XLXN_39,XLXN_26(7),'0','0');
FTCPE_XLXN_41: FTCPE port map (XLXN_41,XLXN_41_T,XLXN_26(7),'0','0');
XLXN_41_T <= (XLXN_39 AND XLXN_40);
FTCPE_XLXN_42: FTCPE port map (XLXN_42,XLXN_42_T,XLXN_26(7),'0','0');
XLXN_42_T <= (XLXN_39 AND XLXN_40 AND XLXN_41);
FTCPE_XLXN_615: FTCPE port map (XLXN_6(15),XLXN_6_T(15),CLK,'0','0');
XLXN_6_T(15) <= (XLXI_3/Q(0) AND XLXI_3/Q(4) AND XLXI_3/Q(8) AND
XLXI_3/Q(12) AND XLXI_3/Q(1) AND XLXI_3/Q(5) AND XLXI_3/Q(9) AND
XLXI_3/Q(10) AND XLXI_3/Q(13) AND XLXI_3/Q(2) AND XLXI_3/Q(6) AND
XLXI_3/Q(11) AND XLXI_3/Q(14) AND XLXI_3/Q(3) AND XLXI_3/Q(7));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC9536XL-5-VQ44
--------------------------------
/44 43 42 41 40 39 38 37 36 35 34 \
| 1 33 |
| 2 32 |
| 3 31 |
| 4 30 |
| 5 XC9536XL-5-VQ44 29 |
| 6 28 |
| 7 27 |
| 8 26 |
| 9 25 |
| 10 24 |
| 11 23 |
\ 12 13 14 15 16 17 18 19 20 21 22 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 23 KPR
2 KPR 24 TDO
3 KPR 25 GND
4 GND 26 VCC
5 CLK 27 KPR
6 KPR 28 KPR
7 KPR 29 KPR
8 KPR 30 KPR
9 TDI 31 KPR
10 TMS 32 KPR
11 TCK 33 KPR
12 KPR 34 KPR
13 KPR 35 VCC
14 KPR 36 KPR
15 VCC 37 KPR
16 KPR 38 KPR
17 GND 39 KPR
18 KPR 40 KPR
19 KPR 41 KPR
20 KPR 42 OUTLED3
21 KPR 43 OUTLED2
22 KPR 44 OUTLED1
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9536xl-5-VQ44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25