Timing Report

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Design Name	CPLDLED
Device, Speed (SpeedFile Version)	XC9536XL, -5 (3.0)
Date Created	Sun May 23 11:20:43 2021
Created By	Timing Report Generator: version P.20131013
Copyright	Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Pad to Pad Delay (tPD)	5.000 ns.

Timing Constraints

Constraint Name	Requirement (ns)	Delay (ns)	Paths	Paths Failing
AUTO_TS_F2F	0.0	0.0	0	0
AUTO_TS_P2P	0.0	5.0	1	1
AUTO_TS_P2F	0.0	0.0	0	0
AUTO_TS_F2P	0.0	0.0	0	0

Constraint: AUTO_TS_F2F

**Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: AUTO_TS_P2P

**Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)
CLK to OUTLED	0.000	5.000	-5.000

Constraint: AUTO_TS_P2F

**Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Constraint: AUTO_TS_F2P

**Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)

Number of constraints not met: 1

Data Sheet Report

Pad to Pad List

Source Pad	Destination Pad	Delay
CLK	OUTLED	5.000

Number of paths analyzed: 1
Number of Timing errors: 1
Analysis Completed: Sun May 23 11:20:43 2021