cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: slow_counter Date: 5-24-2021, 11:52AM
Device Used: XC9536XL-5-VQ44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
34 /36 ( 94%) 97 /180 ( 54%) 53 /108 ( 49%) 27 /36 ( 75%) 8 /34 ( 24%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 28/54 62/90 6/17
FB2 16/18 25/54 35/90 2/17
----- ----- ----- -----
34/36 53/108 97/180 8/34
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 1 1 | I/O : 6 28
Output : 7 7 | GCK/IO : 2 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 8 8
** Power Data **
There are 34 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'slow_counter.ise'.
************************* Summary of Mapped Logic ************************
** 7 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
ssd<4> 2 4 FB1_1 40~ I/O O STD FAST
ssd<3> 5 4 FB1_2 41~ I/O O STD FAST
ssd<1> 4 4 FB1_3 43~ GCK/I/O O STD FAST
ssd<2> 3 4 FB1_4 42~ I/O O STD FAST
ssd<0> 4 4 FB1_5 44~ GCK/I/O O STD FAST
ssd<5> 4 4 FB2_1 39~ I/O O STD FAST
ssd<6> 4 4 FB2_2 38~ I/O O STD FAST
** 27 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
counter2<0> 2 24 FB1_6 STD RESET
counter1<21> 2 22 FB1_7 STD RESET
counter2<2> 3 26 FB1_8 STD RESET
counter1<9> 3 24 FB1_9 STD RESET
counter1<8> 3 24 FB1_10 STD RESET
counter1<22> 3 24 FB1_11 STD RESET
counter1<19> 3 24 FB1_12 STD RESET
counter1<18> 3 24 FB1_13 STD RESET
counter1<14> 3 24 FB1_14 STD RESET
counter1<11> 3 24 FB1_15 STD RESET
counter2<3> 4 28 FB1_16 STD RESET
counter2<1> 4 28 FB1_17 STD RESET
counter1<6> 8 24 FB1_18 STD RESET
counter1<0> 1 1 FB2_5 STD RESET
counter1<7> 2 8 FB2_6 STD RESET
counter1<5> 2 6 FB2_7 STD RESET
counter1<4> 2 5 FB2_8 STD RESET
counter1<3> 2 4 FB2_9 STD RESET
counter1<2> 2 3 FB2_10 STD RESET
counter1<20> 2 21 FB2_11 STD RESET
counter1<1> 2 2 FB2_12 STD RESET
counter1<17> 2 18 FB2_13 STD RESET
counter1<16> 2 17 FB2_14 STD RESET
counter1<15> 2 16 FB2_15 STD RESET
counter1<13> 2 14 FB2_16 STD RESET
counter1<12> 2 13 FB2_17 STD RESET
counter1<10> 2 11 FB2_18 STD RESET
** 1 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk FB1_9 5~ I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 28/26
Number of signals used by logic mapping into function block: 28
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
ssd<4> 2 0 /\2 1 FB1_1 40~ I/O O
ssd<3> 5 0 0 0 FB1_2 41~ I/O O
ssd<1> 4 0 0 1 FB1_3 43~ GCK/I/O O
ssd<2> 3 0 0 2 FB1_4 42~ I/O O
ssd<0> 4 0 0 1 FB1_5 44~ GCK/I/O O
counter2<0> 2 0 0 3 FB1_6 2 I/O (b)
counter1<21> 2 0 0 3 FB1_7 1 GCK/I/O (b)
counter2<2> 3 0 0 2 FB1_8 3 I/O (b)
counter1<9> 3 0 0 2 FB1_9 5 I/O I
counter1<8> 3 0 0 2 FB1_10 6 I/O (b)
counter1<22> 3 0 0 2 FB1_11 7 I/O (b)
counter1<19> 3 0 0 2 FB1_12 8 I/O (b)
counter1<18> 3 0 0 2 FB1_13 12 I/O (b)
counter1<14> 3 0 0 2 FB1_14 13 I/O (b)
counter1<11> 3 0 0 2 FB1_15 14 I/O (b)
counter2<3> 4 0 0 1 FB1_16 16 I/O (b)
counter2<1> 4 0 \/1 0 FB1_17 18 I/O (b)
counter1<6> 8 3<- 0 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 11: counter1<18> 20: counter1<5>
2: counter1<0> 12: counter1<19> 21: counter1<6>
3: counter1<10> 13: counter1<1> 22: counter1<7>
4: counter1<11> 14: counter1<20> 23: counter1<8>
5: counter1<12> 15: counter1<21> 24: counter1<9>
6: counter1<13> 16: counter1<22> 25: counter2<0>
7: counter1<14> 17: counter1<2> 26: counter2<1>
8: counter1<15> 18: counter1<3> 27: counter2<2>
9: counter1<16> 19: counter1<4> 28: counter2<3>
10: counter1<17>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
ssd<4> ........................XXXX............ 4
ssd<3> ........................XXXX............ 4
ssd<1> ........................XXXX............ 4
ssd<2> ........................XXXX............ 4
ssd<0> ........................XXXX............ 4
counter2<0> XXXXXXXXXXXXXXXXXXXXXXXX................ 24
counter1<21> XXXXXXXXXXXXXX..XXXXXXXX................ 22
counter2<2> XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 26
counter1<9> XXXXXXXXXXXXXXXXXXXXXXXX................ 24
counter1<8> XXXXXXXXXXXXXXXXXXXXXXXX................ 24
counter1<22> XXXXXXXXXXXXXXXXXXXXXXXX................ 24
counter1<19> XXXXXXXXXXXXXXXXXXXXXXXX................ 24
counter1<18> XXXXXXXXXXXXXXXXXXXXXXXX................ 24
counter1<14> XXXXXXXXXXXXXXXXXXXXXXXX................ 24
counter1<11> XXXXXXXXXXXXXXXXXXXXXXXX................ 24
counter2<3> XXXXXXXXXXXXXXXXXXXXXXXXXXXX............ 28
counter2<1> XXXXXXXXXXXXXXXXXXXXXXXXXXXX............ 28
counter1<6> XXXXXXXXXXXXXXXXXXXXXXXX................ 24
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 25/29
Number of signals used by logic mapping into function block: 25
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
ssd<5> 4 0 0 1 FB2_1 39~ I/O O
ssd<6> 4 0 0 1 FB2_2 38~ I/O O
(unused) 0 0 0 5 FB2_3 36 GTS/I/O
(unused) 0 0 0 5 FB2_4 37 I/O
counter1<0> 1 0 0 4 FB2_5 34 GTS/I/O (b)
counter1<7> 2 0 0 3 FB2_6 33 GSR/I/O (b)
counter1<5> 2 0 0 3 FB2_7 32 I/O (b)
counter1<4> 2 0 0 3 FB2_8 31 I/O (b)
counter1<3> 2 0 0 3 FB2_9 30 I/O (b)
counter1<2> 2 0 0 3 FB2_10 29 I/O (b)
counter1<20> 2 0 0 3 FB2_11 28 I/O (b)
counter1<1> 2 0 0 3 FB2_12 27 I/O (b)
counter1<17> 2 0 0 3 FB2_13 23 I/O (b)
counter1<16> 2 0 0 3 FB2_14 22 I/O (b)
counter1<15> 2 0 0 3 FB2_15 21 I/O (b)
counter1<13> 2 0 0 3 FB2_16 20 I/O (b)
counter1<12> 2 0 0 3 FB2_17 19 I/O (b)
counter1<10> 2 0 0 3 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 10: counter1<17> 18: counter1<6>
2: counter1<0> 11: counter1<18> 19: counter1<7>
3: counter1<10> 12: counter1<19> 20: counter1<8>
4: counter1<11> 13: counter1<1> 21: counter1<9>
5: counter1<12> 14: counter1<2> 22: counter2<0>
6: counter1<13> 15: counter1<3> 23: counter2<1>
7: counter1<14> 16: counter1<4> 24: counter2<2>
8: counter1<15> 17: counter1<5> 25: counter2<3>
9: counter1<16>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
ssd<5> .....................XXXX............... 4
ssd<6> .....................XXXX............... 4
counter1<0> X....................................... 1
counter1<7> XX..........XXXXXX...................... 8
counter1<5> XX..........XXXX........................ 6
counter1<4> XX..........XXX......................... 5
counter1<3> XX..........XX.......................... 4
counter1<2> XX..........X........................... 3
counter1<20> XXXXXXXXXXXXXXXXXXXXX................... 21
counter1<1> XX...................................... 2
counter1<17> XXXXXXXXX...XXXXXXXXX................... 18
counter1<16> XXXXXXXX....XXXXXXXXX................... 17
counter1<15> XXXXXXX.....XXXXXXXXX................... 16
counter1<13> XXXXX.......XXXXXXXXX................... 14
counter1<12> XXXX........XXXXXXXXX................... 13
counter1<10> XX..........XXXXXXXXX................... 11
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
FTCPE_counter10: FTCPE port map (counter1(0),'1',clk,'0','0');
FTCPE_counter11: FTCPE port map (counter1(1),counter1(0),clk,'0','0');
FTCPE_counter12: FTCPE port map (counter1(2),counter1_T(2),clk,'0','0');
counter1_T(2) <= (counter1(0) AND counter1(1));
FTCPE_counter13: FTCPE port map (counter1(3),counter1_T(3),clk,'0','0');
counter1_T(3) <= (counter1(0) AND counter1(1) AND counter1(2));
FTCPE_counter14: FTCPE port map (counter1(4),counter1_T(4),clk,'0','0');
counter1_T(4) <= (counter1(0) AND counter1(1) AND counter1(2) AND
counter1(3));
FTCPE_counter15: FTCPE port map (counter1(5),counter1_T(5),clk,'0','0');
counter1_T(5) <= (counter1(0) AND counter1(1) AND counter1(2) AND
counter1(3) AND counter1(4));
FTCPE_counter16: FTCPE port map (counter1(6),counter1_T(6),clk,'0','0');
counter1_T(6) <= ((NOT counter1(0))
OR (NOT counter1(1))
OR (NOT counter1(2))
OR (NOT counter1(3))
OR (NOT counter1(5))
OR (NOT counter1(10) AND counter1(11) AND NOT counter1(12) AND
NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND NOT counter1(16) AND
NOT counter1(17) AND counter1(18) AND counter1(19) AND NOT counter1(20) AND
NOT counter1(21) AND NOT counter1(6) AND NOT counter1(7) AND counter1(8) AND
counter1(9) AND counter1(22))
OR (NOT counter1(4)));
FTCPE_counter17: FTCPE port map (counter1(7),counter1_T(7),clk,'0','0');
counter1_T(7) <= (counter1(0) AND counter1(1) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND counter1(6));
FTCPE_counter18: FTCPE port map (counter1(8),counter1_T(8),clk,'0','0');
counter1_T(8) <= ((counter1(0) AND counter1(1) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND counter1(6) AND
counter1(7))
OR (counter1(0) AND NOT counter1(10) AND counter1(11) AND
NOT counter1(12) AND NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND
NOT counter1(16) AND NOT counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND NOT counter1(6) AND
NOT counter1(7) AND counter1(8) AND counter1(9) AND counter1(22)));
FTCPE_counter19: FTCPE port map (counter1(9),counter1_T(9),clk,'0','0');
counter1_T(9) <= ((counter1(0) AND counter1(1) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND counter1(6) AND
counter1(7) AND counter1(8))
OR (counter1(0) AND NOT counter1(10) AND counter1(11) AND
NOT counter1(12) AND NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND
NOT counter1(16) AND NOT counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND NOT counter1(6) AND
NOT counter1(7) AND counter1(8) AND counter1(9) AND counter1(22)));
FTCPE_counter110: FTCPE port map (counter1(10),counter1_T(10),clk,'0','0');
counter1_T(10) <= (counter1(0) AND counter1(1) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND counter1(6) AND
counter1(7) AND counter1(8) AND counter1(9));
FTCPE_counter111: FTCPE port map (counter1(11),counter1_T(11),clk,'0','0');
counter1_T(11) <= ((counter1(0) AND counter1(10) AND counter1(1) AND
counter1(2) AND counter1(3) AND counter1(4) AND counter1(5) AND
counter1(6) AND counter1(7) AND counter1(8) AND counter1(9))
OR (counter1(0) AND NOT counter1(10) AND counter1(11) AND
NOT counter1(12) AND NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND
NOT counter1(16) AND NOT counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND NOT counter1(6) AND
NOT counter1(7) AND counter1(8) AND counter1(9) AND counter1(22)));
FTCPE_counter112: FTCPE port map (counter1(12),counter1_T(12),clk,'0','0');
counter1_T(12) <= (counter1(0) AND counter1(10) AND counter1(11) AND
counter1(1) AND counter1(2) AND counter1(3) AND counter1(4) AND
counter1(5) AND counter1(6) AND counter1(7) AND counter1(8) AND
counter1(9));
FTCPE_counter113: FTCPE port map (counter1(13),counter1_T(13),clk,'0','0');
counter1_T(13) <= (counter1(0) AND counter1(10) AND counter1(11) AND
counter1(12) AND counter1(1) AND counter1(2) AND counter1(3) AND
counter1(4) AND counter1(5) AND counter1(6) AND counter1(7) AND
counter1(8) AND counter1(9));
FTCPE_counter114: FTCPE port map (counter1(14),counter1_T(14),clk,'0','0');
counter1_T(14) <= ((counter1(0) AND counter1(10) AND counter1(11) AND
counter1(12) AND counter1(13) AND counter1(1) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND counter1(6) AND
counter1(7) AND counter1(8) AND counter1(9))
OR (counter1(0) AND NOT counter1(10) AND counter1(11) AND
NOT counter1(12) AND NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND
NOT counter1(16) AND NOT counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND NOT counter1(6) AND
NOT counter1(7) AND counter1(8) AND counter1(9) AND counter1(22)));
FTCPE_counter115: FTCPE port map (counter1(15),counter1_T(15),clk,'0','0');
counter1_T(15) <= (counter1(0) AND counter1(10) AND counter1(11) AND
counter1(12) AND counter1(13) AND counter1(14) AND counter1(1) AND
counter1(2) AND counter1(3) AND counter1(4) AND counter1(5) AND
counter1(6) AND counter1(7) AND counter1(8) AND counter1(9));
FTCPE_counter116: FTCPE port map (counter1(16),counter1_T(16),clk,'0','0');
counter1_T(16) <= (counter1(0) AND counter1(10) AND counter1(11) AND
counter1(12) AND counter1(13) AND counter1(14) AND counter1(15) AND
counter1(1) AND counter1(2) AND counter1(3) AND counter1(4) AND
counter1(5) AND counter1(6) AND counter1(7) AND counter1(8) AND
counter1(9));
FTCPE_counter117: FTCPE port map (counter1(17),counter1_T(17),clk,'0','0');
counter1_T(17) <= (counter1(0) AND counter1(10) AND counter1(11) AND
counter1(12) AND counter1(13) AND counter1(14) AND counter1(15) AND
counter1(16) AND counter1(1) AND counter1(2) AND counter1(3) AND
counter1(4) AND counter1(5) AND counter1(6) AND counter1(7) AND
counter1(8) AND counter1(9));
FTCPE_counter118: FTCPE port map (counter1(18),counter1_T(18),clk,'0','0');
counter1_T(18) <= ((counter1(0) AND counter1(10) AND counter1(11) AND
counter1(12) AND counter1(13) AND counter1(14) AND counter1(15) AND
counter1(16) AND counter1(17) AND counter1(1) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND counter1(6) AND
counter1(7) AND counter1(8) AND counter1(9))
OR (counter1(0) AND NOT counter1(10) AND counter1(11) AND
NOT counter1(12) AND NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND
NOT counter1(16) AND NOT counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND NOT counter1(6) AND
NOT counter1(7) AND counter1(8) AND counter1(9) AND counter1(22)));
FTCPE_counter119: FTCPE port map (counter1(19),counter1_T(19),clk,'0','0');
counter1_T(19) <= ((counter1(0) AND counter1(10) AND counter1(11) AND
counter1(12) AND counter1(13) AND counter1(14) AND counter1(15) AND
counter1(16) AND counter1(17) AND counter1(18) AND counter1(1) AND
counter1(2) AND counter1(3) AND counter1(4) AND counter1(5) AND
counter1(6) AND counter1(7) AND counter1(8) AND counter1(9))
OR (counter1(0) AND NOT counter1(10) AND counter1(11) AND
NOT counter1(12) AND NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND
NOT counter1(16) AND NOT counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND NOT counter1(6) AND
NOT counter1(7) AND counter1(8) AND counter1(9) AND counter1(22)));
FTCPE_counter120: FTCPE port map (counter1(20),counter1_T(20),clk,'0','0');
counter1_T(20) <= (counter1(0) AND counter1(10) AND counter1(11) AND
counter1(12) AND counter1(13) AND counter1(14) AND counter1(15) AND
counter1(16) AND counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND counter1(2) AND counter1(3) AND counter1(4) AND
counter1(5) AND counter1(6) AND counter1(7) AND counter1(8) AND
counter1(9));
FTCPE_counter121: FTCPE port map (counter1(21),counter1_T(21),clk,'0','0');
counter1_T(21) <= (counter1(0) AND counter1(10) AND counter1(11) AND
counter1(12) AND counter1(13) AND counter1(14) AND counter1(15) AND
counter1(16) AND counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND counter1(20) AND counter1(2) AND counter1(3) AND
counter1(4) AND counter1(5) AND counter1(6) AND counter1(7) AND
counter1(8) AND counter1(9));
FTCPE_counter122: FTCPE port map (counter1(22),counter1_T(22),clk,'0','0');
counter1_T(22) <= ((counter1(0) AND counter1(10) AND counter1(11) AND
counter1(12) AND counter1(13) AND counter1(14) AND counter1(15) AND
counter1(16) AND counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND counter1(20) AND counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND counter1(6) AND
counter1(7) AND counter1(8) AND counter1(9))
OR (counter1(0) AND NOT counter1(10) AND counter1(11) AND
NOT counter1(12) AND NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND
NOT counter1(16) AND NOT counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND NOT counter1(6) AND
NOT counter1(7) AND counter1(8) AND counter1(9) AND counter1(22)));
FTCPE_counter20: FTCPE port map (counter2(0),'1',clk,'0','0',counter2_CE(0));
counter2_CE(0) <= (counter1(0) AND NOT counter1(10) AND counter1(11) AND
NOT counter1(12) AND NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND
NOT counter1(16) AND NOT counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND NOT counter1(6) AND
NOT counter1(7) AND counter1(8) AND counter1(9) AND counter1(22));
FTCPE_counter21: FTCPE port map (counter2(1),counter2_T(1),clk,'0','0',counter2_CE(1));
counter2_T(1) <= ((NOT counter2(0))
OR (NOT counter2(1) AND NOT counter2(2) AND counter2(3) AND
counter1(0) AND NOT counter1(10) AND counter1(11) AND NOT counter1(12) AND
NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND NOT counter1(16) AND
NOT counter1(17) AND counter1(18) AND counter1(19) AND counter1(1) AND
NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND counter1(3) AND
counter1(4) AND counter1(5) AND NOT counter1(6) AND NOT counter1(7) AND
counter1(8) AND counter1(9) AND counter1(22)));
counter2_CE(1) <= (counter1(0) AND NOT counter1(10) AND counter1(11) AND
NOT counter1(12) AND NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND
NOT counter1(16) AND NOT counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND NOT counter1(6) AND
NOT counter1(7) AND counter1(8) AND counter1(9) AND counter1(22));
FTCPE_counter22: FTCPE port map (counter2(2),counter2_T(2),clk,'0','0',counter2_CE(2));
counter2_T(2) <= (counter2(1) AND counter2(0));
counter2_CE(2) <= (counter1(0) AND NOT counter1(10) AND counter1(11) AND
NOT counter1(12) AND NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND
NOT counter1(16) AND NOT counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND NOT counter1(6) AND
NOT counter1(7) AND counter1(8) AND counter1(9) AND counter1(22));
FTCPE_counter23: FTCPE port map (counter2(3),counter2_T(3),clk,'0','0',counter2_CE(3));
counter2_T(3) <= ((counter2(1) AND counter2(2) AND counter2(0))
OR (NOT counter2(1) AND NOT counter2(2) AND counter2(0) AND
counter2(3) AND counter1(0) AND NOT counter1(10) AND counter1(11) AND
NOT counter1(12) AND NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND
NOT counter1(16) AND NOT counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND NOT counter1(6) AND
NOT counter1(7) AND counter1(8) AND counter1(9) AND counter1(22)));
counter2_CE(3) <= (counter1(0) AND NOT counter1(10) AND counter1(11) AND
NOT counter1(12) AND NOT counter1(13) AND counter1(14) AND NOT counter1(15) AND
NOT counter1(16) AND NOT counter1(17) AND counter1(18) AND counter1(19) AND
counter1(1) AND NOT counter1(20) AND NOT counter1(21) AND counter1(2) AND
counter1(3) AND counter1(4) AND counter1(5) AND NOT counter1(6) AND
NOT counter1(7) AND counter1(8) AND counter1(9) AND counter1(22));
ssd(0) <= ((counter2(1) AND NOT counter2(3))
OR (NOT counter2(1) AND NOT counter2(2) AND counter2(3))
OR (counter2(2) AND counter2(0) AND NOT counter2(3))
OR (NOT counter2(2) AND NOT counter2(0) AND NOT counter2(3)));
ssd(1) <= ((NOT counter2(1) AND NOT counter2(2))
OR (NOT counter2(2) AND NOT counter2(3))
OR (counter2(1) AND counter2(0) AND NOT counter2(3))
OR (NOT counter2(1) AND NOT counter2(0) AND NOT counter2(3)));
ssd(2) <= ((NOT counter2(1) AND NOT counter2(2))
OR (counter2(2) AND NOT counter2(3))
OR (counter2(0) AND NOT counter2(3)));
ssd(3) <= ((counter2(1) AND NOT counter2(2) AND NOT counter2(3))
OR (counter2(1) AND NOT counter2(0) AND NOT counter2(3))
OR (NOT counter2(1) AND NOT counter2(2) AND counter2(3))
OR (NOT counter2(2) AND NOT counter2(0) AND NOT counter2(3))
OR (NOT counter2(1) AND counter2(2) AND counter2(0) AND
NOT counter2(3)));
ssd(4) <= ((counter2(1) AND NOT counter2(0) AND NOT counter2(3))
OR (NOT counter2(1) AND NOT counter2(2) AND NOT counter2(0)));
ssd(5) <= ((NOT counter2(1) AND counter2(2) AND NOT counter2(3))
OR (NOT counter2(1) AND NOT counter2(2) AND counter2(3))
OR (NOT counter2(1) AND NOT counter2(0) AND NOT counter2(3))
OR (counter2(2) AND NOT counter2(0) AND NOT counter2(3)));
ssd(6) <= ((counter2(1) AND NOT counter2(2) AND NOT counter2(3))
OR (NOT counter2(1) AND counter2(2) AND NOT counter2(3))
OR (NOT counter2(1) AND NOT counter2(2) AND counter2(3))
OR (counter2(2) AND NOT counter2(0) AND NOT counter2(3)));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC9536XL-5-VQ44
--------------------------------
/44 43 42 41 40 39 38 37 36 35 34 \
| 1 33 |
| 2 32 |
| 3 31 |
| 4 30 |
| 5 XC9536XL-5-VQ44 29 |
| 6 28 |
| 7 27 |
| 8 26 |
| 9 25 |
| 10 24 |
| 11 23 |
\ 12 13 14 15 16 17 18 19 20 21 22 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 23 KPR
2 KPR 24 TDO
3 KPR 25 GND
4 GND 26 VCC
5 clk 27 KPR
6 KPR 28 KPR
7 KPR 29 KPR
8 KPR 30 KPR
9 TDI 31 KPR
10 TMS 32 KPR
11 TCK 33 KPR
12 KPR 34 KPR
13 KPR 35 VCC
14 KPR 36 KPR
15 VCC 37 KPR
16 KPR 38 ssd<6>
17 GND 39 ssd<5>
18 KPR 40 ssd<4>
19 KPR 41 ssd<3>
20 KPR 42 ssd<2>
21 KPR 43 ssd<1>
22 KPR 44 ssd<0>
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9536xl-5-VQ44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25