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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:41:19 10/25/2008 
-- Design Name: 
-- Module Name:    villi - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity villi is
    Port ( CLK : in  STD_LOGIC;
           RESET : in  STD_LOGIC;
           count : inout  STD_LOGIC_VECTOR (33 downto 0);
			  clockout : inout STD_LOGIC);
end villi;
--**************************************************************************************
architecture Behavioral of villi is
signal novekvo: std_logic_vector(18 downto 0);
--**************************************************************************************
begin
  osztas: process(RESET,CLK)
  begin
		if (RESET='0') and (CLK='0') then
			count(30)<='1';
		elsif CLK'event then  -- Dual Edge (minden élre beállítva)
			count(30)<='0';
			novekvo <= novekvo + 1;
			If novekvo < "11111111110111000" then
			count(0)<='0';
			count(1)<='0';
			count(2)<='0';
			count(3)<='0';
			count(4)<='0';
			count(5)<='0';
			count(6)<='0';
			count(7)<='0';
			count(8)<='0';
			count(9)<='0';
			count(10)<='0';
			count(11)<='0';
			count(12)<='0';
			count(13)<='0';
			count(14)<='0';
			count(15)<='0';
			count(16)<='0';
			count(17)<='0';
			count(18)<='0';
			count(19)<='0';
			count(20)<='0';
			count(21)<='0';
			count(22)<='0';
			count(23)<='0';
			count(24)<='0';
			count(25)<='0';
			count(26)<='0';
			count(27)<='0';
			count(28)<='0';
			count(29)<='0';
			count(30)<='0';
			count(31)<='0';
			count(32)<='0';
			count(33)<='0';
			end if;
			If novekvo > "11111111110111000" then
			count(0)<='1';
			count(1)<='1';
			count(2)<='1';
			count(3)<='1';
			count(4)<='1';
			count(5)<='1';
			count(6)<='1';
			count(7)<='1';
			count(8)<='1';
			count(9)<='1';
			count(10)<='1';
			count(11)<='1';
			count(12)<='1';
			count(13)<='1';
			count(14)<='1';
			count(15)<='1';
			count(16)<='1';
			count(17)<='1';
			count(18)<='1';
			count(19)<='1';
			count(20)<='1';
			count(21)<='1';
			count(22)<='1';
			count(23)<='1';
			count(24)<='1';
			count(25)<='1';
			count(26)<='1';
			count(27)<='1';
			count(28)<='1';
			count(29)<='1';
			count(30)<='1';
			count(31)<='1';
			count(32)<='1';
			count(33)<='1';
			end if;
		end if;
  end process osztas; 

end Behavioral;