__Lib_TFT_Defs_TFT_Write_Strobe: ;__Lib_TFT_Defs.mbas,97 :: sub procedure TFT_Write_Strobe() ;__Lib_TFT_Defs.mbas,98 :: TFT_WR = 0 _LX INS R2, R0, BitPos(TFT_WR+0), 1 _SX ;__Lib_TFT_Defs.mbas,99 :: asm nop end asm NOP ;__Lib_TFT_Defs.mbas,100 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,101 :: end sub L_end_TFT_Write_Strobe: JR RA NOP ; end of __Lib_TFT_Defs_TFT_Write_Strobe __Lib_TFT_Defs_TFT_Read_Strobe: ;__Lib_TFT_Defs.mbas,103 :: sub procedure TFT_Read_Strobe() ;__Lib_TFT_Defs.mbas,104 :: TFT_RD = 0 _LX INS R2, R0, BitPos(TFT_RD+0), 1 _SX ;__Lib_TFT_Defs.mbas,105 :: asm nop end asm NOP ;__Lib_TFT_Defs.mbas,106 :: asm nop end asm NOP ;__Lib_TFT_Defs.mbas,107 :: asm nop end asm NOP ;__Lib_TFT_Defs.mbas,108 :: asm nop end asm NOP ;__Lib_TFT_Defs.mbas,109 :: asm nop end asm NOP ;__Lib_TFT_Defs.mbas,110 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,111 :: end sub L_end_TFT_Read_Strobe: JR RA NOP ; end of __Lib_TFT_Defs_TFT_Read_Strobe __Lib_TFT_Defs_Read_From_Port: ;__Lib_TFT_Defs.mbas,115 :: dim turnOn as byte ADDIU SP, SP, -4 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,116 :: turnOn = 0 ; turnOn start address is: 12 (R3) MOVZ R3, R0, R0 ;__Lib_TFT_Defs.mbas,117 :: if (PMCON.ON_) then LBU R2, Offset(PMCON+1)(GP) EXT R2, R2, 7, 1 BNE R2, R0, L___Lib_TFT_Defs_Read_From_Port462 NOP J L___Lib_TFT_Defs_Read_From_Port454 NOP L___Lib_TFT_Defs_Read_From_Port462: ; turnOn end address is: 12 (R3) ;__Lib_TFT_Defs.mbas,118 :: PMCON.ON_ = 0 ' MikroE HW (mikromedia for PIC32 with ST7789V controler) will not work if PMP ORI R2, R0, 32768 SW R2, Offset(PMCON+4)(GP) ;__Lib_TFT_Defs.mbas,119 :: turnOn = 1 ' is turnd on. We must turn it off when calling TFT_Read_Strobe function ; turnOn start address is: 12 (R3) ORI R3, R0, 1 ; turnOn end address is: 12 (R3) J L___Lib_TFT_Defs_Read_From_Port4 NOP L___Lib_TFT_Defs_Read_From_Port454: ;__Lib_TFT_Defs.mbas,117 :: if (PMCON.ON_) then ;__Lib_TFT_Defs.mbas,119 :: turnOn = 1 ' is turnd on. We must turn it off when calling TFT_Read_Strobe function L___Lib_TFT_Defs_Read_From_Port4: ;__Lib_TFT_Defs.mbas,122 :: PMCON.ON_ = 0 ; turnOn start address is: 12 (R3) ORI R2, R0, 32768 SW R2, Offset(PMCON+4)(GP) ;__Lib_TFT_Defs.mbas,123 :: dataPort = ^word(@TFT_DataPort - 0x10) LUI R2, hi_addr(TFT_DataPort+0) ORI R2, R2, lo_addr(TFT_DataPort+0) ADDIU R2, R2, -16 ; dataPort start address is: 16 (R4) MOVZ R4, R2, R0 ;__Lib_TFT_Defs.mbas,124 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,125 :: TFT_Read_Strobe() JAL __Lib_TFT_Defs_TFT_Read_Strobe+0 NOP ;__Lib_TFT_Defs.mbas,126 :: Result = dataPort^ LHU R2, 0(R4) ; dataPort end address is: 16 (R4) ; Result start address is: 16 (R4) ANDI R4, R2, 65535 ;__Lib_TFT_Defs.mbas,128 :: if (turnOn) then BNE R3, R0, L___Lib_TFT_Defs_Read_From_Port464 NOP J L___Lib_TFT_Defs_Read_From_Port7 NOP L___Lib_TFT_Defs_Read_From_Port464: ; turnOn end address is: 12 (R3) ;__Lib_TFT_Defs.mbas,129 :: PMCON.ON_ = 1 ORI R2, R0, 32768 SW R2, Offset(PMCON+8)(GP) L___Lib_TFT_Defs_Read_From_Port7: ;__Lib_TFT_Defs.mbas,131 :: end sub ANDI R2, R4, 65535 ; Result end address is: 16 (R4) L_end_Read_From_Port: LW RA, 0(SP) ADDIU SP, SP, 4 JR RA NOP ; end of __Lib_TFT_Defs_Read_From_Port __Lib_TFT_Defs_TFT_Set_DataPort_Direction: ;__Lib_TFT_Defs.mbas,137 :: sub procedure TFT_Set_DataPort_Direction() ;__Lib_TFT_Defs.mbas,140 :: TFT_DataPort_Direction = TFT_DataPort_Direction and not(longword(__controller)) LHU R2, Offset(__Lib_TFT_Defs___controller+0)(GP) NOR R3, R2, R0 LBU R2, Offset(TFT_DataPort_Direction+0)(GP) AND R2, R2, R3 SB R2, Offset(TFT_DataPort_Direction+0)(GP) ;__Lib_TFT_Defs.mbas,141 :: end sub L_end_TFT_Set_DataPort_Direction: JR RA NOP ; end of __Lib_TFT_Defs_TFT_Set_DataPort_Direction __Lib_TFT_Defs_TFT_Set_DataPort_Direction_Input: ;__Lib_TFT_Defs.mbas,147 :: sub procedure TFT_Set_DataPort_Direction_Input() ;__Lib_TFT_Defs.mbas,150 :: TFT_DataPort_Direction = TFT_DataPort_Direction or (longword(__controller)) LHU R3, Offset(__Lib_TFT_Defs___controller+0)(GP) LBU R2, Offset(TFT_DataPort_Direction+0)(GP) OR R2, R2, R3 SB R2, Offset(TFT_DataPort_Direction+0)(GP) ;__Lib_TFT_Defs.mbas,151 :: end sub L_end_TFT_Set_DataPort_Direction_Input: JR RA NOP ; end of __Lib_TFT_Defs_TFT_Set_DataPort_Direction_Input _TFT_Set_Index: ;__Lib_TFT_Defs.mbas,157 :: sub procedure TFT_Set_Index(dim index as byte) ADDIU SP, SP, -4 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,158 :: TFT_RS = 0 _LX INS R2, R0, BitPos(TFT_RS+0), 1 _SX ;__Lib_TFT_Defs.mbas,159 :: TFT_DataPort = index SB R25, Offset(TFT_DataPort+0)(GP) ;__Lib_TFT_Defs.mbas,160 :: TFT_Write_Strobe() JAL __Lib_TFT_Defs_TFT_Write_Strobe+0 NOP ;__Lib_TFT_Defs.mbas,161 :: end sub L_end_TFT_Set_Index: LW RA, 0(SP) ADDIU SP, SP, 4 JR RA NOP ; end of _TFT_Set_Index _TFT_Write_Command: ;__Lib_TFT_Defs.mbas,167 :: sub procedure TFT_Write_Command(dim cmd as byte) ADDIU SP, SP, -4 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,168 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,169 :: TFT_DataPort = cmd SB R25, Offset(TFT_DataPort+0)(GP) ;__Lib_TFT_Defs.mbas,170 :: TFT_Write_Strobe() JAL __Lib_TFT_Defs_TFT_Write_Strobe+0 NOP ;__Lib_TFT_Defs.mbas,171 :: end sub L_end_TFT_Write_Command: LW RA, 0(SP) ADDIU SP, SP, 4 JR RA NOP ; end of _TFT_Write_Command _TFT_Set_Reg: ;__Lib_TFT_Defs.mbas,178 :: sub procedure TFT_Set_Reg(dim index, value as byte) ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,179 :: TFT_CS = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,180 :: TFT_Set_Index_Ptr(index) SB R26, 8(SP) LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LBU R26, 8(SP) ;__Lib_TFT_Defs.mbas,181 :: TFT_Write_Command_Ptr(value) ANDI R25, R26, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,182 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,183 :: end sub L_end_TFT_Set_Reg: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_Set_Reg _TFT_Reset_Device: ;__Lib_TFT_Defs.mbas,189 :: sub procedure TFT_Reset_Device() ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,191 :: TFT_RST = 0 SW R25, 4(SP) SW R26, 8(SP) _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,193 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,196 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,198 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,201 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,203 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,205 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,206 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,207 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,208 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,211 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,212 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,213 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,214 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,217 :: TFT_Set_Reg(0xEA, 0x00) ' PTBA[15:8] MOVZ R26, R0, R0 ORI R25, R0, 234 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,218 :: TFT_Set_Reg(0xEB, 0x20) ' PTBA[7:0] ORI R26, R0, 32 ORI R25, R0, 235 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,219 :: TFT_Set_Reg(0xEC, 0x0C) ' STBA[15:8] ORI R26, R0, 12 ORI R25, R0, 236 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,220 :: TFT_Set_Reg(0xED, 0xC4) ' STBA[7:0] ORI R26, R0, 196 ORI R25, R0, 237 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,221 :: TFT_Set_Reg(0xE8, 0x40) ' OPON[7:0] ORI R26, R0, 64 ORI R25, R0, 232 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,222 :: TFT_Set_Reg(0xE9, 0x38) ' OPON1[7:0] ORI R26, R0, 56 ORI R25, R0, 233 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,223 :: TFT_Set_Reg(0xF1, 0x01) ' OTPS1B ORI R26, R0, 1 ORI R25, R0, 241 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,224 :: TFT_Set_Reg(0xF2, 0x10) ' GEN ORI R26, R0, 16 ORI R25, R0, 242 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,225 :: TFT_Set_Reg(0x27, 0xA3) ORI R26, R0, 163 ORI R25, R0, 39 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,228 :: TFT_Set_Reg(0x40, 0x00) ' MOVZ R26, R0, R0 ORI R25, R0, 64 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,229 :: TFT_Set_Reg(0x41, 0x00) ' MOVZ R26, R0, R0 ORI R25, R0, 65 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,230 :: TFT_Set_Reg(0x42, 0x01) ' ORI R26, R0, 1 ORI R25, R0, 66 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,231 :: TFT_Set_Reg(0x43, 0x13) ' ORI R26, R0, 19 ORI R25, R0, 67 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,232 :: TFT_Set_Reg(0x44, 0x10) ' ORI R26, R0, 16 ORI R25, R0, 68 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,233 :: TFT_Set_Reg(0x45, 0x26) ' ORI R26, R0, 38 ORI R25, R0, 69 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,234 :: TFT_Set_Reg(0x46, 0x08) ' ORI R26, R0, 8 ORI R25, R0, 70 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,235 :: TFT_Set_Reg(0x47, 0x51) ' ORI R26, R0, 81 ORI R25, R0, 71 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,236 :: TFT_Set_Reg(0x48, 0x02) ' ORI R26, R0, 2 ORI R25, R0, 72 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,237 :: TFT_Set_Reg(0x49, 0x12) ' ORI R26, R0, 18 ORI R25, R0, 73 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,238 :: TFT_Set_Reg(0x4A, 0x18) ' ORI R26, R0, 24 ORI R25, R0, 74 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,239 :: TFT_Set_Reg(0x4B, 0x19) ' ORI R26, R0, 25 ORI R25, R0, 75 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,240 :: TFT_Set_Reg(0x4C, 0x14) ' ORI R26, R0, 20 ORI R25, R0, 76 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,242 :: TFT_Set_Reg(0x50, 0x19) ' ORI R26, R0, 25 ORI R25, R0, 80 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,243 :: TFT_Set_Reg(0x51, 0x2F) ' ORI R26, R0, 47 ORI R25, R0, 81 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,244 :: TFT_Set_Reg(0x52, 0x2C) ' ORI R26, R0, 44 ORI R25, R0, 82 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,245 :: TFT_Set_Reg(0x53, 0x3E) ' ORI R26, R0, 62 ORI R25, R0, 83 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,246 :: TFT_Set_Reg(0x54, 0x3F) ' ORI R26, R0, 63 ORI R25, R0, 84 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,247 :: TFT_Set_Reg(0x55, 0x3F) ' ORI R26, R0, 63 ORI R25, R0, 85 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,248 :: TFT_Set_Reg(0x56, 0x2E) ' ORI R26, R0, 46 ORI R25, R0, 86 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,249 :: TFT_Set_Reg(0x57, 0x77) ' ORI R26, R0, 119 ORI R25, R0, 87 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,250 :: TFT_Set_Reg(0x58, 0x0B) ' ORI R26, R0, 11 ORI R25, R0, 88 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,251 :: TFT_Set_Reg(0x59, 0x06) ' ORI R26, R0, 6 ORI R25, R0, 89 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,252 :: TFT_Set_Reg(0x5A, 0x07) ' ORI R26, R0, 7 ORI R25, R0, 90 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,253 :: TFT_Set_Reg(0x5B, 0x0D) ' ORI R26, R0, 13 ORI R25, R0, 91 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,254 :: TFT_Set_Reg(0x5C, 0x1D) ' ORI R26, R0, 29 ORI R25, R0, 92 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,255 :: TFT_Set_Reg(0x5D, 0xCC) ' ORI R26, R0, 204 ORI R25, R0, 93 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,258 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L__TFT_Reset_Device471 NOP J L__TFT_Reset_Device16 NOP L__TFT_Reset_Device471: ;__Lib_TFT_Defs.mbas,259 :: TFT_Set_Reg(0x04, 0x00) MOVZ R26, R0, R0 ORI R25, R0, 4 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,260 :: TFT_Set_Reg(0x05, 0xEF) ORI R26, R0, 239 ORI R25, R0, 5 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,261 :: TFT_Set_Reg(0x08, 0x01) ORI R26, R0, 1 ORI R25, R0, 8 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,262 :: TFT_Set_Reg(0x09, 0x3F) ORI R26, R0, 63 ORI R25, R0, 9 JAL _TFT_Set_Reg+0 NOP J L__TFT_Reset_Device17 NOP ;__Lib_TFT_Defs.mbas,263 :: else L__TFT_Reset_Device16: ;__Lib_TFT_Defs.mbas,264 :: TFT_Set_Reg(0x04, 0x01) ORI R26, R0, 1 ORI R25, R0, 4 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,265 :: TFT_Set_Reg(0x05, 0x3F) ORI R26, R0, 63 ORI R25, R0, 5 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,266 :: TFT_Set_Reg(0x08, 0x00) MOVZ R26, R0, R0 ORI R25, R0, 8 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,267 :: TFT_Set_Reg(0x09, 0xEF) ORI R26, R0, 239 ORI R25, R0, 9 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,268 :: end if L__TFT_Reset_Device17: ;__Lib_TFT_Defs.mbas,270 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L__TFT_Reset_Device472 NOP J L__TFT_Reset_Device19 NOP L__TFT_Reset_Device472: ;__Lib_TFT_Defs.mbas,271 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L__TFT_Reset_Device473 NOP J L__TFT_Reset_Device22 NOP L__TFT_Reset_Device473: ;__Lib_TFT_Defs.mbas,272 :: TFT_Set_Reg(0x16, 0xC8) ' MY=1, MX=1, MV=0, BGR=1 ORI R26, R0, 200 ORI R25, R0, 22 JAL _TFT_Set_Reg+0 NOP J L__TFT_Reset_Device23 NOP ;__Lib_TFT_Defs.mbas,273 :: else L__TFT_Reset_Device22: ;__Lib_TFT_Defs.mbas,274 :: TFT_Set_Reg(0x16, 0x08) ' MY=0, MX=0, MV=0, BGR=1 ORI R26, R0, 8 ORI R25, R0, 22 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,275 :: end if L__TFT_Reset_Device23: J L__TFT_Reset_Device20 NOP ;__Lib_TFT_Defs.mbas,276 :: else L__TFT_Reset_Device19: ;__Lib_TFT_Defs.mbas,277 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L__TFT_Reset_Device474 NOP J L__TFT_Reset_Device25 NOP L__TFT_Reset_Device474: ;__Lib_TFT_Defs.mbas,278 :: TFT_Set_Reg(0x16, 0xA8) ' MY=0, MX=1, MV=1, BGR=1 ORI R26, R0, 168 ORI R25, R0, 22 JAL _TFT_Set_Reg+0 NOP J L__TFT_Reset_Device26 NOP ;__Lib_TFT_Defs.mbas,279 :: else L__TFT_Reset_Device25: ;__Lib_TFT_Defs.mbas,280 :: TFT_Set_Reg(0x16, 0x68) ' MY=1, MX=0, MV=1, BGR=1 ORI R26, R0, 104 ORI R25, R0, 22 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,281 :: end if L__TFT_Reset_Device26: ;__Lib_TFT_Defs.mbas,282 :: end if L__TFT_Reset_Device20: ;__Lib_TFT_Defs.mbas,285 :: TFT_Set_Reg(0x1B, 0x1B) ' VRH = 4.65 ORI R26, R0, 27 ORI R25, R0, 27 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,286 :: TFT_Set_Reg(0x1A, 0x01) ' BT ORI R26, R0, 1 ORI R25, R0, 26 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,287 :: TFT_Set_Reg(0x24, 0x2F) ' VMH ORI R26, R0, 47 ORI R25, R0, 36 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,288 :: TFT_Set_Reg(0x25, 0x57) ' VML ORI R26, R0, 87 ORI R25, R0, 37 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,291 :: TFT_Set_Reg(0x23, 0x8D) ' FLICKER ADJUST ORI R26, R0, 141 ORI R25, R0, 35 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,294 :: TFT_Set_Reg(0x18, 0x36) ' ORI R26, R0, 54 ORI R25, R0, 24 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,295 :: TFT_Set_Reg(0x19, 0x01) ' ORI R26, R0, 1 ORI R25, R0, 25 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,296 :: TFT_Set_Reg(0x01, 0x00) ' MOVZ R26, R0, R0 ORI R25, R0, 1 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,297 :: TFT_Set_Reg(0x1F, 0x88) ' ORI R26, R0, 136 ORI R25, R0, 31 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,298 :: Delay_5ms() JAL _Delay_5ms+0 NOP ;__Lib_TFT_Defs.mbas,299 :: TFT_Set_Reg(0x1F, 0x80) ' ORI R26, R0, 128 ORI R25, R0, 31 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,300 :: Delay_5ms() JAL _Delay_5ms+0 NOP ;__Lib_TFT_Defs.mbas,301 :: TFT_Set_Reg(0x1F, 0x90) ' ORI R26, R0, 144 ORI R25, R0, 31 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,302 :: Delay_5ms() JAL _Delay_5ms+0 NOP ;__Lib_TFT_Defs.mbas,303 :: TFT_Set_Reg(0x1F, 0xD0) ' ORI R26, R0, 208 ORI R25, R0, 31 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,304 :: Delay_5ms() JAL _Delay_5ms+0 NOP ;__Lib_TFT_Defs.mbas,307 :: TFT_Set_Reg(0x17, 0x05) ' ORI R26, R0, 5 ORI R25, R0, 23 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,310 :: TFT_Set_Reg(0x36, 0x00) ' Panel characteristic control register MOVZ R26, R0, R0 ORI R25, R0, 54 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,313 :: TFT_Set_Reg(0x28, 0x38) ' ORI R26, R0, 56 ORI R25, R0, 40 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,314 :: Delay_10ms()Delay_10ms()Delay_10ms()Delay_10ms() JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,315 :: TFT_Set_Reg(0x28, 0x3C) ' ORI R26, R0, 60 ORI R25, R0, 40 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,316 :: end sub L_end_TFT_Reset_Device: LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_Reset_Device _TFT_Set_Address: ;__Lib_TFT_Defs.mbas,323 :: sub procedure TFT_Set_Address(dim x, y as word) ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,324 :: TFT_Set_Index_Ptr(0x02) SW R25, 4(SP) SH R26, 8(SP) SH R25, 10(SP) ORI R25, R0, 2 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,325 :: TFT_Write_Command_Ptr(Hi(x)) SH R25, 10(SP) EXT R25, R25, 8, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,326 :: TFT_Set_Index_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,327 :: TFT_Write_Command_Ptr(Lo(x)) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,328 :: TFT_Set_Index_Ptr(0x06) ORI R25, R0, 6 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,329 :: TFT_Write_Command_Ptr(Hi(y)) SH R26, 8(SP) EXT R25, R26, 8, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,330 :: TFT_Set_Index_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,331 :: TFT_Write_Command_Ptr(Lo(y)) ANDI R25, R26, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,332 :: TFT_Set_Index_Ptr(0x22) ORI R25, R0, 34 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,333 :: end sub L_end_TFT_Set_Address: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_Set_Address _TFT_Write_Data: ;__Lib_TFT_Defs.mbas,341 :: sub procedure TFT_Write_Data(dim _data as word) ADDIU SP, SP, -4 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,342 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,343 :: TFT_DataPort = Hi(_data) EXT R2, R25, 8, 8 SB R2, Offset(TFT_DataPort+0)(GP) ;__Lib_TFT_Defs.mbas,344 :: TFT_Write_Strobe() JAL __Lib_TFT_Defs_TFT_Write_Strobe+0 NOP ;__Lib_TFT_Defs.mbas,345 :: TFT_DataPort = Lo(_data) SB R25, Offset(TFT_DataPort+0)(GP) ;__Lib_TFT_Defs.mbas,346 :: TFT_Write_Strobe() JAL __Lib_TFT_Defs_TFT_Write_Strobe+0 NOP ;__Lib_TFT_Defs.mbas,347 :: end sub L_end_TFT_Write_Data: LW RA, 0(SP) ADDIU SP, SP, 4 JR RA NOP ; end of _TFT_Write_Data _TFT_16bit_Write_Data: ;__Lib_TFT_Defs.mbas,356 :: dim temp as ^word ADDIU SP, SP, -4 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,357 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,358 :: temp = @TFT_DataPort ; temp start address is: 8 (R2) LUI R2, hi_addr(TFT_DataPort+0) ORI R2, R2, lo_addr(TFT_DataPort+0) ;__Lib_TFT_Defs.mbas,359 :: temp^ = _data SH R25, 0(R2) ; temp end address is: 8 (R2) ;__Lib_TFT_Defs.mbas,360 :: TFT_Write_Strobe() JAL __Lib_TFT_Defs_TFT_Write_Strobe+0 NOP ;__Lib_TFT_Defs.mbas,361 :: end sub L_end_TFT_16bit_Write_Data: LW RA, 0(SP) ADDIU SP, SP, 4 JR RA NOP ; end of _TFT_16bit_Write_Data _TFT_Init: ;__Lib_TFT_Defs.mbas,368 :: sub procedure TFT_Init(dim display_width, display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,369 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,370 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init480 NOP J L__TFT_Init32 NOP L__TFT_Init480: ;__Lib_TFT_Defs.mbas,371 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,372 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,373 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init32: ;__Lib_TFT_Defs.mbas,376 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,377 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,378 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init481 NOP J L__TFT_Init35 NOP L__TFT_Init481: ;__Lib_TFT_Defs.mbas,379 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init36 NOP ;__Lib_TFT_Defs.mbas,380 :: else L__TFT_Init35: ;__Lib_TFT_Defs.mbas,381 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,382 :: end if L__TFT_Init36: ;__Lib_TFT_Defs.mbas,384 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,385 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,386 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,388 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,389 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,391 :: TFT_Reset_Device() JAL _TFT_Reset_Device+0 NOP ;__Lib_TFT_Defs.mbas,392 :: TFT_Set_Address_Ptr = @TFT_Set_Address LUI R2, hi_addr(_TFT_Set_Address+0) ORI R2, R2, lo_addr(_TFT_Set_Address+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,393 :: end sub L_end_TFT_Init: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init _TFT_Init_Custom: ;__Lib_TFT_Defs.mbas,403 :: sub procedure TFT_Init_Custom(dim display_width, display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,404 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,405 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_Custom484 NOP J L__TFT_Init_Custom39 NOP L__TFT_Init_Custom484: ;__Lib_TFT_Defs.mbas,406 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,407 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,408 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_Custom39: ;__Lib_TFT_Defs.mbas,411 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,412 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,413 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_Custom485 NOP J L__TFT_Init_Custom42 NOP L__TFT_Init_Custom485: ;__Lib_TFT_Defs.mbas,414 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_Custom43 NOP ;__Lib_TFT_Defs.mbas,415 :: else L__TFT_Init_Custom42: ;__Lib_TFT_Defs.mbas,416 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,417 :: end if L__TFT_Init_Custom43: ;__Lib_TFT_Defs.mbas,419 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,420 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,421 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,423 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,425 :: TFT_Reset_Device() 'return JAL _TFT_Reset_Device+0 NOP ;__Lib_TFT_Defs.mbas,426 :: TFT_Set_Address_Ptr = @TFT_Set_Address LUI R2, hi_addr(_TFT_Set_Address+0) ORI R2, R2, lo_addr(_TFT_Set_Address+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,427 :: end sub L_end_TFT_Init_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_Custom _TFT_Set_Address_R61526: ;__Lib_TFT_Defs.mbas,435 :: sub procedure TFT_Set_Address_R61526(dim x as word y as word) ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,436 :: TFT_Set_Index_Ptr(0x2A) SW R25, 4(SP) SH R26, 8(SP) SH R25, 10(SP) ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,437 :: TFT_Write_Command_Ptr(Hi(x)) SH R25, 10(SP) EXT R25, R25, 8, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,438 :: TFT_Write_Command_Ptr(x) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,439 :: TFT_Set_Index_Ptr(0x2B) ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,440 :: TFT_Write_Command_Ptr(Hi(y)) SH R26, 8(SP) EXT R25, R26, 8, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,441 :: TFT_Write_Command_Ptr(y) ANDI R25, R26, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,442 :: TFT_Set_Index_Ptr(0x2C) ORI R25, R0, 44 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,443 :: end sub L_end_TFT_Set_Address_R61526: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_Set_Address_R61526 __Lib_TFT_Defs_TFT_Reset_R61526: ;__Lib_TFT_Defs.mbas,449 :: sub procedure TFT_Reset_R61526() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,451 :: TFT_RST = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,453 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,456 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,458 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,461 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,463 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,465 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,466 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,467 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,468 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,471 :: Delay_1ms() JAL _Delay_1ms+0 NOP ;__Lib_TFT_Defs.mbas,472 :: TFT_RST = 0 _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,473 :: Delay_10ms() JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,474 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,475 :: Delay_100ms() Delay_10ms() Delay_10ms() Delay_10ms() JAL _Delay_100ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,477 :: TFT_CS = 0 _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,479 :: TFT_Set_Index_Ptr(0xB0)'Manufacturer Command Access Protect ORI R25, R0, 176 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,480 :: TFT_Write_Command_Ptr(0x3F) ORI R25, R0, 63 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,481 :: TFT_Write_Command_Ptr(0x3F) ORI R25, R0, 63 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,482 :: Delay_100ms() Delay_100ms() Delay_10ms() Delay_10ms() JAL _Delay_100ms+0 NOP JAL _Delay_100ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,483 :: Delay_10ms() Delay_10ms() Delay_10ms() Delay_10ms() JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,485 :: TFT_Set_Index_Ptr(0xFE) ORI R25, R0, 254 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,486 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,487 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,488 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,489 :: TFT_Write_Command_Ptr(0x21) ORI R25, R0, 33 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,490 :: TFT_Write_Command_Ptr(0xB4) ORI R25, R0, 180 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,492 :: TFT_Set_Index_Ptr(0xB3)'Frame Memory Access and Interface Setting ORI R25, R0, 179 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,493 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,494 :: TFT_Write_Command_Ptr(0x10) ORI R25, R0, 16 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,496 :: TFT_Set_Index_Ptr(0xE0)'NVM Access Control ORI R25, R0, 224 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,497 :: TFT_Write_Command_Ptr(0x00)'NVAE: NVM access enable register. NVM access is enabled when NVAE=1. MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,498 :: TFT_Write_Command_Ptr(0x40)'FTT: NVM control bit. ORI R25, R0, 64 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,499 :: Delay_100ms() Delay_100ms() JAL _Delay_100ms+0 NOP JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,501 :: TFT_Set_Index_Ptr(0xB3) ORI R25, R0, 179 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,502 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,503 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,505 :: TFT_Set_Index_Ptr(0xFE) ORI R25, R0, 254 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,506 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,507 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,508 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,509 :: TFT_Write_Command_Ptr(0x21) ORI R25, R0, 33 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,510 :: TFT_Write_Command_Ptr(0x30) ORI R25, R0, 48 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,512 :: TFT_Set_Index_Ptr(0xB0) ORI R25, R0, 176 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,513 :: TFT_Write_Command_Ptr(0x3F) ORI R25, R0, 63 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,514 :: TFT_Write_Command_Ptr(0x3F) ORI R25, R0, 63 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,516 :: TFT_Set_Index_Ptr(0xB3) ORI R25, R0, 179 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,517 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,518 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,519 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,520 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,522 :: TFT_Set_Index_Ptr(0xB4) ORI R25, R0, 180 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,523 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,525 :: TFT_Set_Index_Ptr(0xC0) ORI R25, R0, 192 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,526 :: TFT_Write_Command_Ptr(0x03)'GIP REV SM GS BGR SS ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,527 :: TFT_Write_Command_Ptr(0x4F) ORI R25, R0, 79 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,528 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,529 :: TFT_Write_Command_Ptr(0x10) ORI R25, R0, 16 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,530 :: TFT_Write_Command_Ptr(0xA0)'BLV=0 LINE ORI R25, R0, 160 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,531 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,532 :: TFT_Write_Command_Ptr(0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,533 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,535 :: TFT_Set_Index_Ptr(0xC1) ORI R25, R0, 193 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,536 :: TFT_Write_Command_Ptr(0x01)'BC0 Frame inversion(0)/Line inversion(1) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,537 :: TFT_Write_Command_Ptr(0x02)'DIV0[1:0] 800kHz ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,538 :: TFT_Write_Command_Ptr(0x20)'RTN0[5:0] clocks 21 ORI R25, R0, 32 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,539 :: TFT_Write_Command_Ptr(0x06)'BP0[7:0] 6 lines ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,540 :: TFT_Write_Command_Ptr(0x06)'FP0[7:0] 6 lines ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,541 :: Delay_100ms() Delay_100ms() JAL _Delay_100ms+0 NOP JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,543 :: TFT_Set_Index_Ptr(0xC3) 'PRTIAL MODE ORI R25, R0, 195 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,544 :: TFT_Write_Command_Ptr(0x01)'BC2 ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,545 :: TFT_Write_Command_Ptr(0x00)'DIV2[1:0] MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,546 :: TFT_Write_Command_Ptr(0x21)'RTN2[5:0] ORI R25, R0, 33 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,547 :: TFT_Write_Command_Ptr(0x08)'BP2[7:0] ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,548 :: TFT_Write_Command_Ptr(0x08)'FP2[7:0] ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,549 :: Delay_100ms() Delay_100ms() JAL _Delay_100ms+0 NOP JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,551 :: TFT_Set_Index_Ptr(0xC4) ORI R25, R0, 196 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,552 :: TFT_Write_Command_Ptr(0x11) ORI R25, R0, 17 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,553 :: TFT_Write_Command_Ptr(0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,554 :: TFT_Write_Command_Ptr(0x43) ORI R25, R0, 67 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,555 :: TFT_Write_Command_Ptr(0x04) ORI R25, R0, 4 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,557 :: TFT_Set_Index_Ptr(0x0c8) ORI R25, R0, 200 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,558 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,559 :: TFT_Write_Command_Ptr(0x0D) ORI R25, R0, 13 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,560 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,561 :: TFT_Write_Command_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,562 :: TFT_Write_Command_Ptr(0x16) ORI R25, R0, 22 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,563 :: TFT_Write_Command_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,564 :: TFT_Write_Command_Ptr(0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,565 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,566 :: TFT_Write_Command_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,567 :: TFT_Write_Command_Ptr(0x06) ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,568 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,569 :: TFT_Write_Command_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,570 :: TFT_Write_Command_Ptr(0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,571 :: TFT_Write_Command_Ptr(0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,572 :: TFT_Write_Command_Ptr(0x0E) ORI R25, R0, 14 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,573 :: TFT_Write_Command_Ptr(0x12) ORI R25, R0, 18 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,574 :: TFT_Write_Command_Ptr(0x12) ORI R25, R0, 18 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,575 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,576 :: TFT_Write_Command_Ptr(0x10) ORI R25, R0, 16 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,577 :: TFT_Write_Command_Ptr(0x04) ORI R25, R0, 4 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,578 :: TFT_Write_Command_Ptr(0x0D) ORI R25, R0, 13 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,579 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,581 :: TFT_Set_Index_Ptr(0x0c9) ORI R25, R0, 201 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,582 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,583 :: TFT_Write_Command_Ptr(0x0D) ORI R25, R0, 13 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,584 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,585 :: TFT_Write_Command_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,586 :: TFT_Write_Command_Ptr(0x16) ORI R25, R0, 22 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,587 :: TFT_Write_Command_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,588 :: TFT_Write_Command_Ptr(0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,589 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,590 :: TFT_Write_Command_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,591 :: TFT_Write_Command_Ptr(0x06) ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,592 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,593 :: TFT_Write_Command_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,594 :: TFT_Write_Command_Ptr(0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,595 :: TFT_Write_Command_Ptr(0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,596 :: TFT_Write_Command_Ptr(0x0E) ORI R25, R0, 14 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,597 :: TFT_Write_Command_Ptr(0x12) ORI R25, R0, 18 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,598 :: TFT_Write_Command_Ptr(0x12) ORI R25, R0, 18 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,599 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,600 :: TFT_Write_Command_Ptr(0x10) ORI R25, R0, 16 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,601 :: TFT_Write_Command_Ptr(0x04) ORI R25, R0, 4 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,602 :: TFT_Write_Command_Ptr(0x0D) ORI R25, R0, 13 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,603 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,605 :: TFT_Set_Index_Ptr(0x0ca) ORI R25, R0, 202 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,606 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,607 :: TFT_Write_Command_Ptr(0x0D) ORI R25, R0, 13 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,608 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,609 :: TFT_Write_Command_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,610 :: TFT_Write_Command_Ptr(0x16) ORI R25, R0, 22 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,611 :: TFT_Write_Command_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,612 :: TFT_Write_Command_Ptr(0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,613 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,614 :: TFT_Write_Command_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,615 :: TFT_Write_Command_Ptr(0x06) ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,616 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,617 :: TFT_Write_Command_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,618 :: TFT_Write_Command_Ptr(0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,619 :: TFT_Write_Command_Ptr(0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,620 :: TFT_Write_Command_Ptr(0x0E) ORI R25, R0, 14 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,621 :: TFT_Write_Command_Ptr(0x12) ORI R25, R0, 18 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,622 :: TFT_Write_Command_Ptr(0x12) ORI R25, R0, 18 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,623 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,624 :: TFT_Write_Command_Ptr(0x10) ORI R25, R0, 16 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,625 :: TFT_Write_Command_Ptr(0x04) ORI R25, R0, 4 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,626 :: TFT_Write_Command_Ptr(0x0D) ORI R25, R0, 13 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,627 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,629 :: TFT_Set_Index_Ptr(0x0cB) ORI R25, R0, 203 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,630 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,631 :: TFT_Write_Command_Ptr(0x0D) ORI R25, R0, 13 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,632 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,633 :: TFT_Write_Command_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,634 :: TFT_Write_Command_Ptr(0x16) ORI R25, R0, 22 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,635 :: TFT_Write_Command_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,636 :: TFT_Write_Command_Ptr(0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,637 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,638 :: TFT_Write_Command_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,639 :: TFT_Write_Command_Ptr(0x06) ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,640 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,641 :: TFT_Write_Command_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,642 :: TFT_Write_Command_Ptr(0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,643 :: TFT_Write_Command_Ptr(0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,644 :: TFT_Write_Command_Ptr(0x0E) ORI R25, R0, 14 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,645 :: TFT_Write_Command_Ptr(0x12) ORI R25, R0, 18 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,646 :: TFT_Write_Command_Ptr(0x12) ORI R25, R0, 18 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,647 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,648 :: TFT_Write_Command_Ptr(0x10) ORI R25, R0, 16 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,649 :: TFT_Write_Command_Ptr(0x04) ORI R25, R0, 4 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,650 :: TFT_Write_Command_Ptr(0x0D) ORI R25, R0, 13 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,651 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,653 :: TFT_Set_Index_Ptr(0xD0) ORI R25, R0, 208 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,654 :: TFT_Write_Command_Ptr(0x63) ORI R25, R0, 99 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,655 :: TFT_Write_Command_Ptr(0x53) ORI R25, R0, 83 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,656 :: TFT_Write_Command_Ptr(0x82)'VC2[2:0]=010,VCI2=5V ORI R25, R0, 130 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,657 :: TFT_Write_Command_Ptr(0x33)'33,VREG=4.7V ORI R25, R0, 51 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,659 :: TFT_Set_Index_Ptr(0xD1) ORI R25, R0, 209 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,660 :: TFT_Write_Command_Ptr(0x60)'VCOMH=VREG x 0.876 69 ORI R25, R0, 96 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,661 :: TFT_Write_Command_Ptr(0x69)'VDV=VREG x 1.064 ORI R25, R0, 105 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,663 :: TFT_Set_Index_Ptr(0xD2)'DC10[2:0], DC12[2:0] ORI R25, R0, 210 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,664 :: TFT_Write_Command_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,665 :: TFT_Write_Command_Ptr(0x24) ORI R25, R0, 36 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,667 :: TFT_Set_Index_Ptr(0xD4) ORI R25, R0, 212 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,668 :: TFT_Write_Command_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,669 :: TFT_Write_Command_Ptr(0x24) ORI R25, R0, 36 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,671 :: TFT_Set_Index_Ptr(0xE2)'NVM Load Control ORI R25, R0, 226 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,672 :: TFT_Write_Command_Ptr(0x3F) ORI R25, R0, 63 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,674 :: TFT_Set_Index_Ptr(0x35)'set_tear_on ORI R25, R0, 53 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,675 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,677 :: TFT_Set_Index_Ptr(0x36) ORI R25, R0, 54 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,678 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_R61526488 NOP J L___Lib_TFT_Defs_TFT_Reset_R6152647 NOP L___Lib_TFT_Defs_TFT_Reset_R61526488: ;__Lib_TFT_Defs.mbas,679 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_R61526489 NOP J L___Lib_TFT_Defs_TFT_Reset_R6152650 NOP L___Lib_TFT_Defs_TFT_Reset_R61526489: ;__Lib_TFT_Defs.mbas,680 :: TFT_Write_Command_Ptr(0xC0) ORI R25, R0, 192 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_R6152651 NOP ;__Lib_TFT_Defs.mbas,681 :: else L___Lib_TFT_Defs_TFT_Reset_R6152650: ;__Lib_TFT_Defs.mbas,682 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,683 :: end if L___Lib_TFT_Defs_TFT_Reset_R6152651: J L___Lib_TFT_Defs_TFT_Reset_R6152648 NOP ;__Lib_TFT_Defs.mbas,684 :: else L___Lib_TFT_Defs_TFT_Reset_R6152647: ;__Lib_TFT_Defs.mbas,685 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_R61526490 NOP J L___Lib_TFT_Defs_TFT_Reset_R6152653 NOP L___Lib_TFT_Defs_TFT_Reset_R61526490: ;__Lib_TFT_Defs.mbas,686 :: TFT_Write_Command_Ptr(0x70) ORI R25, R0, 112 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_R6152654 NOP ;__Lib_TFT_Defs.mbas,687 :: else L___Lib_TFT_Defs_TFT_Reset_R6152653: ;__Lib_TFT_Defs.mbas,688 :: TFT_Write_Command_Ptr(0x21) ORI R25, R0, 33 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,689 :: end if L___Lib_TFT_Defs_TFT_Reset_R6152654: ;__Lib_TFT_Defs.mbas,690 :: end if L___Lib_TFT_Defs_TFT_Reset_R6152648: ;__Lib_TFT_Defs.mbas,692 :: TFT_Set_Index_Ptr(0x3A) 'set_pixel_format ORI R25, R0, 58 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,693 :: TFT_Write_Command_Ptr(0x55) ORI R25, R0, 85 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,695 :: TFT_Set_Index_Ptr(0x2A) 'set_column_address ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,696 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,697 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,698 :: TFT_Write_Command_Ptr((TFT_DISP_WIDTH-1) >> 8) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) ADDIU R2, R2, -1 ANDI R2, R2, 65535 SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,699 :: TFT_Write_Command_Ptr(TFT_DISP_WIDTH-1) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) ADDIU R2, R2, -1 ANDI R25, R2, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,701 :: TFT_Set_Index_Ptr(0x2B) 'set_page_address: ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,702 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,703 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,704 :: TFT_Write_Command_Ptr((TFT_DISP_HEIGHT-1) >> 8) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) ADDIU R2, R2, -1 ANDI R2, R2, 65535 SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,705 :: TFT_Write_Command_Ptr(TFT_DISP_HEIGHT-1) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) ADDIU R2, R2, -1 ANDI R25, R2, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,707 :: TFT_Set_Index_Ptr(0x2C) 'write_memory_start: ORI R25, R0, 44 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,708 :: TFT_Set_Index_Ptr(0x11) 'exit_sleep_mode ORI R25, R0, 17 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,709 :: Delay_100ms() Delay_100ms() JAL _Delay_100ms+0 NOP JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,710 :: TFT_Set_Index_Ptr(0x29) 'set_display_on ORI R25, R0, 41 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,711 :: Delay_100ms() Delay_100ms() JAL _Delay_100ms+0 NOP JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,713 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,714 :: end sub L_end_TFT_Reset_R61526: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of __Lib_TFT_Defs_TFT_Reset_R61526 _TFT_Init_R61526: ;__Lib_TFT_Defs.mbas,721 :: sub procedure TFT_Init_R61526(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,722 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,723 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_R61526493 NOP J L__TFT_Init_R6152657 NOP L__TFT_Init_R61526493: ;__Lib_TFT_Defs.mbas,724 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,725 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,726 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_R6152657: ;__Lib_TFT_Defs.mbas,729 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,730 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,731 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_R61526494 NOP J L__TFT_Init_R6152660 NOP L__TFT_Init_R61526494: ;__Lib_TFT_Defs.mbas,732 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_R6152661 NOP ;__Lib_TFT_Defs.mbas,733 :: else L__TFT_Init_R6152660: ;__Lib_TFT_Defs.mbas,734 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,735 :: end if L__TFT_Init_R6152661: ;__Lib_TFT_Defs.mbas,737 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,738 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,740 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,741 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,742 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,744 :: TFT_Reset_R61526() JAL __Lib_TFT_Defs_TFT_Reset_R61526+0 NOP ;__Lib_TFT_Defs.mbas,745 :: TFT_Set_Address_Ptr = @TFT_Set_Address_R61526 LUI R2, hi_addr(_TFT_Set_Address_R61526+0) ORI R2, R2, lo_addr(_TFT_Set_Address_R61526+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,746 :: end sub L_end_TFT_Init_R61526: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_R61526 _TFT_Init_R61526_Custom: ;__Lib_TFT_Defs.mbas,756 :: sub procedure TFT_Init_R61526_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,757 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,758 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_R61526_Custom497 NOP J L__TFT_Init_R61526_Custom64 NOP L__TFT_Init_R61526_Custom497: ;__Lib_TFT_Defs.mbas,759 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,760 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,761 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_R61526_Custom64: ;__Lib_TFT_Defs.mbas,764 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,765 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,766 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_R61526_Custom498 NOP J L__TFT_Init_R61526_Custom67 NOP L__TFT_Init_R61526_Custom498: ;__Lib_TFT_Defs.mbas,767 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_R61526_Custom68 NOP ;__Lib_TFT_Defs.mbas,768 :: else L__TFT_Init_R61526_Custom67: ;__Lib_TFT_Defs.mbas,769 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,770 :: end if L__TFT_Init_R61526_Custom68: ;__Lib_TFT_Defs.mbas,772 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,773 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,775 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,776 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,778 :: TFT_Reset_R61526() JAL __Lib_TFT_Defs_TFT_Reset_R61526+0 NOP ;__Lib_TFT_Defs.mbas,779 :: TFT_Set_Address_Ptr = @TFT_Set_Address_R61526 LUI R2, hi_addr(_TFT_Set_Address_R61526+0) ORI R2, R2, lo_addr(_TFT_Set_Address_R61526+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,780 :: end sub L_end_TFT_Init_R61526_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_R61526_Custom _TFT_Set_Address_SST7715R: ;__Lib_TFT_Defs.mbas,789 :: sub procedure TFT_Set_Address_SST7715R(dim x as word y as word) ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,790 :: TFT_Set_Index_Ptr(0x2A) SW R25, 4(SP) SH R26, 8(SP) SH R25, 10(SP) ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,791 :: TFT_Write_Command_Ptr(x >> 8) ANDI R2, R25, 65535 SRL R2, R2, 8 SH R25, 10(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,792 :: TFT_Write_Command_Ptr(x) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,793 :: TFT_Set_Index_Ptr(0x2B) ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,794 :: TFT_Write_Command_Ptr(y >> 8) ANDI R2, R26, 65535 SRL R2, R2, 8 SH R26, 8(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,795 :: TFT_Write_Command_Ptr(y) ANDI R25, R26, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,796 :: TFT_Set_Index_Ptr(0x2C) ORI R25, R0, 44 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,797 :: end sub L_end_TFT_Set_Address_SST7715R: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_Set_Address_SST7715R __Lib_TFT_Defs_TFT_Reset_SST7715R: ;__Lib_TFT_Defs.mbas,803 :: sub procedure TFT_Reset_SST7715R() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,805 :: TFT_RST = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,807 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,810 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,812 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,815 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,817 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,819 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,820 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,821 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,822 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,825 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,826 :: Delay_1ms() JAL _Delay_1ms+0 NOP ;__Lib_TFT_Defs.mbas,827 :: TFT_RST = 0 _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,828 :: Delay_10ms() JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,829 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,830 :: Delay_100ms() Delay_10ms() Delay_10ms() JAL _Delay_100ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,832 :: TFT_CS = 0 _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,834 :: TFT_Set_Index_Ptr(0x11) 'Exit Sleep ORI R25, R0, 17 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,835 :: Delay_100ms() Delay_10ms() Delay_10ms() Delay_10ms() JAL _Delay_100ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,837 :: TFT_Set_Index_Ptr(0xB1) ORI R25, R0, 177 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,838 :: TFT_Write_Command_Ptr(0x02) ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,839 :: TFT_Write_Command_Ptr(0x23) ORI R25, R0, 35 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,840 :: TFT_Write_Command_Ptr(0x22) ORI R25, R0, 34 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,842 :: TFT_Set_Index_Ptr(0xB2) ORI R25, R0, 178 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,843 :: TFT_Write_Command_Ptr(0x02) ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,844 :: TFT_Write_Command_Ptr(0x23) ORI R25, R0, 35 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,845 :: TFT_Write_Command_Ptr(0x22) ORI R25, R0, 34 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,847 :: TFT_Set_Index_Ptr(0xB3) ORI R25, R0, 179 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,848 :: TFT_Write_Command_Ptr(0x02) ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,849 :: TFT_Write_Command_Ptr(0x23) ORI R25, R0, 35 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,850 :: TFT_Write_Command_Ptr(0x22) ORI R25, R0, 34 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,851 :: TFT_Write_Command_Ptr(0x02) ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,852 :: TFT_Write_Command_Ptr(0x23) ORI R25, R0, 35 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,853 :: TFT_Write_Command_Ptr(0x22) ORI R25, R0, 34 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,855 :: TFT_Set_Index_Ptr(0xB4) ORI R25, R0, 180 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,856 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,858 :: TFT_Set_Index_Ptr(0xC0) ORI R25, R0, 192 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,859 :: TFT_Write_Command_Ptr(0xA3) ORI R25, R0, 163 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,860 :: TFT_Write_Command_Ptr(0x02) ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,861 :: TFT_Write_Command_Ptr(0x84) ORI R25, R0, 132 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,863 :: TFT_Set_Index_Ptr(0xC1) ORI R25, R0, 193 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,864 :: TFT_Write_Command_Ptr(0xC5) ORI R25, R0, 197 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,866 :: TFT_Set_Index_Ptr(0xC2) ORI R25, R0, 194 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,867 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,868 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,870 :: TFT_Set_Index_Ptr(0xC3) ORI R25, R0, 195 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,871 :: TFT_Write_Command_Ptr(0x8A) ORI R25, R0, 138 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,872 :: TFT_Write_Command_Ptr(0x2A) ORI R25, R0, 42 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,874 :: TFT_Set_Index_Ptr(0xC4) ORI R25, R0, 196 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,875 :: TFT_Write_Command_Ptr(0x8A) ORI R25, R0, 138 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,876 :: TFT_Write_Command_Ptr(0xEE) ORI R25, R0, 238 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,878 :: TFT_Set_Index_Ptr(0xC5) ORI R25, R0, 197 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,879 :: TFT_Write_Command_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,881 :: TFT_Set_Index_Ptr(0x36) ORI R25, R0, 54 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,882 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_SST7715R501 NOP J L___Lib_TFT_Defs_TFT_Reset_SST7715R72 NOP L___Lib_TFT_Defs_TFT_Reset_SST7715R501: ;__Lib_TFT_Defs.mbas,883 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_SST7715R502 NOP J L___Lib_TFT_Defs_TFT_Reset_SST7715R75 NOP L___Lib_TFT_Defs_TFT_Reset_SST7715R502: ;__Lib_TFT_Defs.mbas,884 :: TFT_Write_Command_Ptr(0xA0) ORI R25, R0, 160 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_SST7715R76 NOP ;__Lib_TFT_Defs.mbas,885 :: else L___Lib_TFT_Defs_TFT_Reset_SST7715R75: ;__Lib_TFT_Defs.mbas,886 :: TFT_Write_Command_Ptr(0x60) ORI R25, R0, 96 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,887 :: end if L___Lib_TFT_Defs_TFT_Reset_SST7715R76: J L___Lib_TFT_Defs_TFT_Reset_SST7715R73 NOP ;__Lib_TFT_Defs.mbas,888 :: else L___Lib_TFT_Defs_TFT_Reset_SST7715R72: ;__Lib_TFT_Defs.mbas,889 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_SST7715R503 NOP J L___Lib_TFT_Defs_TFT_Reset_SST7715R78 NOP L___Lib_TFT_Defs_TFT_Reset_SST7715R503: ;__Lib_TFT_Defs.mbas,890 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_SST7715R79 NOP ;__Lib_TFT_Defs.mbas,891 :: else L___Lib_TFT_Defs_TFT_Reset_SST7715R78: ;__Lib_TFT_Defs.mbas,892 :: TFT_Write_Command_Ptr(0xC0) ORI R25, R0, 192 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,893 :: end if L___Lib_TFT_Defs_TFT_Reset_SST7715R79: ;__Lib_TFT_Defs.mbas,894 :: end if L___Lib_TFT_Defs_TFT_Reset_SST7715R73: ;__Lib_TFT_Defs.mbas,896 :: TFT_Set_Index_Ptr(0x3A) ORI R25, R0, 58 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,897 :: TFT_Write_Command_Ptr(0x55) ' RGB 565 ORI R25, R0, 85 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,899 :: TFT_Set_Index_Ptr(0xF0) ORI R25, R0, 240 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,900 :: TFT_Write_Command_Ptr(0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,902 :: TFT_Set_Index_Ptr(0xF6) ORI R25, R0, 246 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,903 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,905 :: TFT_Set_Index_Ptr(0xE0) ORI R25, R0, 224 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,906 :: TFT_Write_Command_Ptr(0x03)'p1 ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,907 :: TFT_Write_Command_Ptr(0x1B)'p2 ORI R25, R0, 27 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,908 :: TFT_Write_Command_Ptr(0x09)'p3 ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,909 :: TFT_Write_Command_Ptr(0x0E)'p4 ORI R25, R0, 14 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,910 :: TFT_Write_Command_Ptr(0x32)'p5 ORI R25, R0, 50 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,911 :: TFT_Write_Command_Ptr(0x2D)'p6 ORI R25, R0, 45 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,912 :: TFT_Write_Command_Ptr(0x28)'p7 ORI R25, R0, 40 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,913 :: TFT_Write_Command_Ptr(0x2C)'p8 ORI R25, R0, 44 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,914 :: TFT_Write_Command_Ptr(0x2B)'p9 ORI R25, R0, 43 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,915 :: TFT_Write_Command_Ptr(0x29)'p10 ORI R25, R0, 41 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,916 :: TFT_Write_Command_Ptr(0x30)'p11 ORI R25, R0, 48 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,917 :: TFT_Write_Command_Ptr(0x3B)'p12 ORI R25, R0, 59 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,918 :: TFT_Write_Command_Ptr(0x00)'p13 MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,919 :: TFT_Write_Command_Ptr(0x01)'p14 ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,920 :: TFT_Write_Command_Ptr(0x02)'p15 ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,921 :: TFT_Write_Command_Ptr(0x10)'p16 ORI R25, R0, 16 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,923 :: TFT_Set_Index_Ptr(0xE1) ORI R25, R0, 225 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,924 :: TFT_Write_Command_Ptr(0x03)'p1 ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,925 :: TFT_Write_Command_Ptr(0x1B)'p2 ORI R25, R0, 27 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,926 :: TFT_Write_Command_Ptr(0x09)'p3 ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,927 :: TFT_Write_Command_Ptr(0x0E)'p4 ORI R25, R0, 14 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,928 :: TFT_Write_Command_Ptr(0x32)'p5 ORI R25, R0, 50 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,929 :: TFT_Write_Command_Ptr(0x2E)'p6 ORI R25, R0, 46 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,930 :: TFT_Write_Command_Ptr(0x28)'p7 ORI R25, R0, 40 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,931 :: TFT_Write_Command_Ptr(0x2C)'p8 ORI R25, R0, 44 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,932 :: TFT_Write_Command_Ptr(0x2B)'p9 ORI R25, R0, 43 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,933 :: TFT_Write_Command_Ptr(0x28)'p10 ORI R25, R0, 40 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,934 :: TFT_Write_Command_Ptr(0x31)'p11 ORI R25, R0, 49 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,935 :: TFT_Write_Command_Ptr(0x3C)'p12 ORI R25, R0, 60 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,936 :: TFT_Write_Command_Ptr(0x00)'p13 MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,937 :: TFT_Write_Command_Ptr(0x00)'p14 MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,938 :: TFT_Write_Command_Ptr(0x02)'p15 ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,939 :: TFT_Write_Command_Ptr(0x10)'p15 ORI R25, R0, 16 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,941 :: TFT_Set_Index_Ptr(0x13) ' Normal Display Mode On ORI R25, R0, 19 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,942 :: TFT_Set_Index_Ptr(0x20) ' Display inversion OFF ORI R25, R0, 32 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,943 :: TFT_Set_Index_Ptr(0x29) ' Display ON ORI R25, R0, 41 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,944 :: TFT_Set_Index_Ptr(0x38) ' Idle Mode Off ORI R25, R0, 56 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,945 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,947 :: TFT_Set_Index_Ptr(0x2A) 'set_column_address ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,948 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,949 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,950 :: TFT_Write_Command_Ptr(Hi(TFT_DISP_WIDTH-1)) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) ADDIU R2, R2, -1 EXT R25, R2, 8, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,951 :: TFT_Write_Command_Ptr(TFT_DISP_WIDTH-1) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) ADDIU R2, R2, -1 ANDI R25, R2, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,953 :: TFT_Set_Index_Ptr(0x2B) ' set_page_address: ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,954 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,955 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,956 :: TFT_Write_Command_Ptr(Hi(TFT_DISP_HEIGHT-1)) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) ADDIU R2, R2, -1 EXT R25, R2, 8, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,957 :: TFT_Write_Command_Ptr(TFT_DISP_HEIGHT-1) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) ADDIU R2, R2, -1 ANDI R25, R2, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,959 :: TFT_Set_Index_Ptr(0x2C) ORI R25, R0, 44 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,960 :: Delay_10ms() JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,962 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,963 :: end sub L_end_TFT_Reset_SST7715R: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of __Lib_TFT_Defs_TFT_Reset_SST7715R _TFT_Init_SST7715R: ;__Lib_TFT_Defs.mbas,970 :: sub procedure TFT_Init_SST7715R(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,971 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,972 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_SST7715R506 NOP J L__TFT_Init_SST7715R82 NOP L__TFT_Init_SST7715R506: ;__Lib_TFT_Defs.mbas,973 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,974 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,975 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_SST7715R82: ;__Lib_TFT_Defs.mbas,978 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,979 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,980 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_SST7715R507 NOP J L__TFT_Init_SST7715R85 NOP L__TFT_Init_SST7715R507: ;__Lib_TFT_Defs.mbas,981 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_SST7715R86 NOP ;__Lib_TFT_Defs.mbas,982 :: else L__TFT_Init_SST7715R85: ;__Lib_TFT_Defs.mbas,983 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,984 :: end if L__TFT_Init_SST7715R86: ;__Lib_TFT_Defs.mbas,986 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,987 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,989 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,990 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,991 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,993 :: TFT_Reset_SST7715R() JAL __Lib_TFT_Defs_TFT_Reset_SST7715R+0 NOP ;__Lib_TFT_Defs.mbas,994 :: TFT_Set_Address_Ptr = @TFT_Set_Address_SST7715R LUI R2, hi_addr(_TFT_Set_Address_SST7715R+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SST7715R+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,995 :: end sub L_end_TFT_Init_SST7715R: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_SST7715R _TFT_Init_SST7715R_Custom: ;__Lib_TFT_Defs.mbas,1005 :: sub procedure TFT_Init_SST7715R_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1006 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,1007 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_SST7715R_Custom510 NOP J L__TFT_Init_SST7715R_Custom89 NOP L__TFT_Init_SST7715R_Custom510: ;__Lib_TFT_Defs.mbas,1008 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1009 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1010 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_SST7715R_Custom89: ;__Lib_TFT_Defs.mbas,1013 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,1014 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,1015 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_SST7715R_Custom511 NOP J L__TFT_Init_SST7715R_Custom92 NOP L__TFT_Init_SST7715R_Custom511: ;__Lib_TFT_Defs.mbas,1016 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_SST7715R_Custom93 NOP ;__Lib_TFT_Defs.mbas,1017 :: else L__TFT_Init_SST7715R_Custom92: ;__Lib_TFT_Defs.mbas,1018 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,1019 :: end if L__TFT_Init_SST7715R_Custom93: ;__Lib_TFT_Defs.mbas,1021 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,1022 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,1024 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,1025 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,1027 :: TFT_Reset_SST7715R() JAL __Lib_TFT_Defs_TFT_Reset_SST7715R+0 NOP ;__Lib_TFT_Defs.mbas,1028 :: TFT_Set_Address_Ptr = @TFT_Set_Address_SST7715R LUI R2, hi_addr(_TFT_Set_Address_SST7715R+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SST7715R+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1029 :: end sub L_end_TFT_Init_SST7715R_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_SST7715R_Custom __Lib_TFT_Defs_TFT_Reset_HX8347G: ;__Lib_TFT_Defs.mbas,1037 :: sub procedure TFT_Reset_HX8347G() ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1039 :: TFT_RST = 0 SW R25, 4(SP) SW R26, 8(SP) _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,1041 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1044 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,1046 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1049 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,1051 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1053 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1054 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1055 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,1056 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,1059 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,1060 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,1061 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,1062 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,1064 :: TFT_Set_Reg(0xEA, 0x00) ' PTBA[15:8] MOVZ R26, R0, R0 ORI R25, R0, 234 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1065 :: TFT_Set_Reg(0xEB, 0x20) ' PTBA[7:0] ORI R26, R0, 32 ORI R25, R0, 235 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1066 :: TFT_Set_Reg(0xEC, 0x0C) ' STBA[15:8] ORI R26, R0, 12 ORI R25, R0, 236 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1067 :: TFT_Set_Reg(0xED, 0xC4) ' STBA[7:0] ORI R26, R0, 196 ORI R25, R0, 237 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1068 :: TFT_Set_Reg(0xE8, 0x40) ' OPON[7:0] ORI R26, R0, 64 ORI R25, R0, 232 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1069 :: TFT_Set_Reg(0xE9, 0x38) ' OPON1[7:0] ORI R26, R0, 56 ORI R25, R0, 233 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1070 :: TFT_Set_Reg(0xF1, 0x01) ' OTPS1B ORI R26, R0, 1 ORI R25, R0, 241 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1071 :: TFT_Set_Reg(0xF2, 0x10) ' GEN ORI R26, R0, 16 ORI R25, R0, 242 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1072 :: TFT_Set_Reg(0x27, 0xA3) ORI R26, R0, 163 ORI R25, R0, 39 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1075 :: TFT_Set_Reg(0x40, 0x00) ' MOVZ R26, R0, R0 ORI R25, R0, 64 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1076 :: TFT_Set_Reg(0x41, 0x00) ' MOVZ R26, R0, R0 ORI R25, R0, 65 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1077 :: TFT_Set_Reg(0x42, 0x01) ' ORI R26, R0, 1 ORI R25, R0, 66 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1078 :: TFT_Set_Reg(0x43, 0x13) ' ORI R26, R0, 19 ORI R25, R0, 67 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1079 :: TFT_Set_Reg(0x44, 0x10) ' ORI R26, R0, 16 ORI R25, R0, 68 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1080 :: TFT_Set_Reg(0x45, 0x26) ' ORI R26, R0, 38 ORI R25, R0, 69 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1081 :: TFT_Set_Reg(0x46, 0x08) ' ORI R26, R0, 8 ORI R25, R0, 70 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1082 :: TFT_Set_Reg(0x47, 0x51) ' ORI R26, R0, 81 ORI R25, R0, 71 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1083 :: TFT_Set_Reg(0x48, 0x02) ' ORI R26, R0, 2 ORI R25, R0, 72 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1084 :: TFT_Set_Reg(0x49, 0x12) ' ORI R26, R0, 18 ORI R25, R0, 73 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1085 :: TFT_Set_Reg(0x4A, 0x18) ' ORI R26, R0, 24 ORI R25, R0, 74 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1086 :: TFT_Set_Reg(0x4B, 0x19) ' ORI R26, R0, 25 ORI R25, R0, 75 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1087 :: TFT_Set_Reg(0x4C, 0x14) ' ORI R26, R0, 20 ORI R25, R0, 76 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1089 :: TFT_Set_Reg(0x50, 0x19) ' ORI R26, R0, 25 ORI R25, R0, 80 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1090 :: TFT_Set_Reg(0x51, 0x2F) ' ORI R26, R0, 47 ORI R25, R0, 81 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1091 :: TFT_Set_Reg(0x52, 0x2C) ' ORI R26, R0, 44 ORI R25, R0, 82 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1092 :: TFT_Set_Reg(0x53, 0x3E) ' ORI R26, R0, 62 ORI R25, R0, 83 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1093 :: TFT_Set_Reg(0x54, 0x3F) ' ORI R26, R0, 63 ORI R25, R0, 84 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1094 :: TFT_Set_Reg(0x55, 0x3F) ' ORI R26, R0, 63 ORI R25, R0, 85 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1095 :: TFT_Set_Reg(0x56, 0x2E) ' ORI R26, R0, 46 ORI R25, R0, 86 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1096 :: TFT_Set_Reg(0x57, 0x77) ' ORI R26, R0, 119 ORI R25, R0, 87 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1097 :: TFT_Set_Reg(0x58, 0x0B) ' ORI R26, R0, 11 ORI R25, R0, 88 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1098 :: TFT_Set_Reg(0x59, 0x06) ' ORI R26, R0, 6 ORI R25, R0, 89 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1099 :: TFT_Set_Reg(0x5A, 0x07) ' ORI R26, R0, 7 ORI R25, R0, 90 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1100 :: TFT_Set_Reg(0x5B, 0x0D) ' ORI R26, R0, 13 ORI R25, R0, 91 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1101 :: TFT_Set_Reg(0x5C, 0x1D) ' ORI R26, R0, 29 ORI R25, R0, 92 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1102 :: TFT_Set_Reg(0x5D, 0xCC) ' ORI R26, R0, 204 ORI R25, R0, 93 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1105 :: TFT_Set_Reg(0x04, (TFT_DISP_WIDTH-1) >> 8) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) ADDIU R2, R2, -1 ANDI R2, R2, 65535 SRL R2, R2, 8 ANDI R26, R2, 65535 ORI R25, R0, 4 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1106 :: TFT_Set_Reg(0x05, TFT_DISP_WIDTH-1) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) ADDIU R2, R2, -1 ANDI R26, R2, 255 ORI R25, R0, 5 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1107 :: TFT_Set_Reg(0x08, (TFT_DISP_HEIGHT-1) >> 8) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) ADDIU R2, R2, -1 ANDI R2, R2, 65535 SRL R2, R2, 8 ANDI R26, R2, 65535 ORI R25, R0, 8 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1108 :: TFT_Set_Reg(0x09, TFT_DISP_HEIGHT-1) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) ADDIU R2, R2, -1 ANDI R26, R2, 255 ORI R25, R0, 9 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1110 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_HX8347G513 NOP J L___Lib_TFT_Defs_TFT_Reset_HX8347G96 NOP L___Lib_TFT_Defs_TFT_Reset_HX8347G513: ;__Lib_TFT_Defs.mbas,1111 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_HX8347G514 NOP J L___Lib_TFT_Defs_TFT_Reset_HX8347G99 NOP L___Lib_TFT_Defs_TFT_Reset_HX8347G514: ;__Lib_TFT_Defs.mbas,1112 :: TFT_Set_Reg(0x16, 0x88) ' MY=1, MX=0, MV=0, BGR=1 ORI R26, R0, 136 ORI R25, R0, 22 JAL _TFT_Set_Reg+0 NOP J L___Lib_TFT_Defs_TFT_Reset_HX8347G100 NOP ;__Lib_TFT_Defs.mbas,1113 :: else L___Lib_TFT_Defs_TFT_Reset_HX8347G99: ;__Lib_TFT_Defs.mbas,1114 :: TFT_Set_Reg(0x16, 0x48) ' MY=0, MX=1, MV=0, BGR=1 ORI R26, R0, 72 ORI R25, R0, 22 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1115 :: end if L___Lib_TFT_Defs_TFT_Reset_HX8347G100: J L___Lib_TFT_Defs_TFT_Reset_HX8347G97 NOP ;__Lib_TFT_Defs.mbas,1116 :: else L___Lib_TFT_Defs_TFT_Reset_HX8347G96: ;__Lib_TFT_Defs.mbas,1117 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_HX8347G515 NOP J L___Lib_TFT_Defs_TFT_Reset_HX8347G102 NOP L___Lib_TFT_Defs_TFT_Reset_HX8347G515: ;__Lib_TFT_Defs.mbas,1118 :: TFT_Set_Reg(0x16, 0xE8) ' MY=1, MX=1, MV=1, BGR=1 ORI R26, R0, 232 ORI R25, R0, 22 JAL _TFT_Set_Reg+0 NOP J L___Lib_TFT_Defs_TFT_Reset_HX8347G103 NOP ;__Lib_TFT_Defs.mbas,1119 :: else L___Lib_TFT_Defs_TFT_Reset_HX8347G102: ;__Lib_TFT_Defs.mbas,1120 :: TFT_Set_Reg(0x16, 0x28) ' MY=0, MX=0, MV=1, BGR=1 ORI R26, R0, 40 ORI R25, R0, 22 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1121 :: end if L___Lib_TFT_Defs_TFT_Reset_HX8347G103: ;__Lib_TFT_Defs.mbas,1122 :: end if L___Lib_TFT_Defs_TFT_Reset_HX8347G97: ;__Lib_TFT_Defs.mbas,1125 :: TFT_Set_Reg(0x1B, 0x1B) ' VRH = 4.65 ORI R26, R0, 27 ORI R25, R0, 27 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1126 :: TFT_Set_Reg(0x1A, 0x01) ' BT ORI R26, R0, 1 ORI R25, R0, 26 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1127 :: TFT_Set_Reg(0x24, 0x2F) ' VMH ORI R26, R0, 47 ORI R25, R0, 36 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1128 :: TFT_Set_Reg(0x25, 0x57) ' VML ORI R26, R0, 87 ORI R25, R0, 37 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1131 :: TFT_Set_Reg(0x23, 0x8D) ' FLICKER ADJUST ORI R26, R0, 141 ORI R25, R0, 35 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1134 :: TFT_Set_Reg(0x18, 0x36) ' ORI R26, R0, 54 ORI R25, R0, 24 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1135 :: TFT_Set_Reg(0x19, 0x01) ' ORI R26, R0, 1 ORI R25, R0, 25 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1136 :: TFT_Set_Reg(0x01, 0x00) ' MOVZ R26, R0, R0 ORI R25, R0, 1 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1137 :: TFT_Set_Reg(0x1F, 0x88) ' ORI R26, R0, 136 ORI R25, R0, 31 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1138 :: Delay_5ms() JAL _Delay_5ms+0 NOP ;__Lib_TFT_Defs.mbas,1139 :: TFT_Set_Reg(0x1F, 0x80) ' ORI R26, R0, 128 ORI R25, R0, 31 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1140 :: Delay_5ms() JAL _Delay_5ms+0 NOP ;__Lib_TFT_Defs.mbas,1141 :: TFT_Set_Reg(0x1F, 0x90) ' ORI R26, R0, 144 ORI R25, R0, 31 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1142 :: Delay_5ms() JAL _Delay_5ms+0 NOP ;__Lib_TFT_Defs.mbas,1143 :: TFT_Set_Reg(0x1F, 0xD0) ' ORI R26, R0, 208 ORI R25, R0, 31 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1144 :: Delay_5ms() JAL _Delay_5ms+0 NOP ;__Lib_TFT_Defs.mbas,1147 :: TFT_Set_Reg(0x17, 0x05) ' ORI R26, R0, 5 ORI R25, R0, 23 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1150 :: TFT_Set_Reg(0x36, 0x00) ' Panel characteristic control register MOVZ R26, R0, R0 ORI R25, R0, 54 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1153 :: TFT_Set_Reg(0x28, 0x38) ' ORI R26, R0, 56 ORI R25, R0, 40 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1154 :: Delay_10ms() JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1155 :: Delay_10ms() JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1156 :: Delay_10ms() JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1157 :: Delay_10ms() JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1158 :: TFT_Set_Reg(0x28, 0x3C) ' ORI R26, R0, 60 ORI R25, R0, 40 JAL _TFT_Set_Reg+0 NOP ;__Lib_TFT_Defs.mbas,1159 :: end sub L_end_TFT_Reset_HX8347G: LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of __Lib_TFT_Defs_TFT_Reset_HX8347G _TFT_Init_HX8347G: ;__Lib_TFT_Defs.mbas,1166 :: sub procedure TFT_Init_HX8347G(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1167 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,1168 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_HX8347G518 NOP J L__TFT_Init_HX8347G106 NOP L__TFT_Init_HX8347G518: ;__Lib_TFT_Defs.mbas,1169 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1170 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1171 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_HX8347G106: ;__Lib_TFT_Defs.mbas,1174 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,1175 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,1176 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_HX8347G519 NOP J L__TFT_Init_HX8347G109 NOP L__TFT_Init_HX8347G519: ;__Lib_TFT_Defs.mbas,1177 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_HX8347G110 NOP ;__Lib_TFT_Defs.mbas,1178 :: else L__TFT_Init_HX8347G109: ;__Lib_TFT_Defs.mbas,1179 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,1180 :: end if L__TFT_Init_HX8347G110: ;__Lib_TFT_Defs.mbas,1182 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,1183 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,1185 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,1186 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,1187 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,1189 :: TFT_Reset_HX8347G() JAL __Lib_TFT_Defs_TFT_Reset_HX8347G+0 NOP ;__Lib_TFT_Defs.mbas,1190 :: TFT_Set_Address_Ptr = @TFT_Set_Address LUI R2, hi_addr(_TFT_Set_Address+0) ORI R2, R2, lo_addr(_TFT_Set_Address+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1191 :: end sub L_end_TFT_Init_HX8347G: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_HX8347G _TFT_Init_HX8347G_Custom: ;__Lib_TFT_Defs.mbas,1201 :: sub procedure TFT_Init_HX8347G_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1202 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,1203 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_HX8347G_Custom522 NOP J L__TFT_Init_HX8347G_Custom113 NOP L__TFT_Init_HX8347G_Custom522: ;__Lib_TFT_Defs.mbas,1204 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1205 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1206 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_HX8347G_Custom113: ;__Lib_TFT_Defs.mbas,1209 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,1210 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,1211 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_HX8347G_Custom523 NOP J L__TFT_Init_HX8347G_Custom116 NOP L__TFT_Init_HX8347G_Custom523: ;__Lib_TFT_Defs.mbas,1212 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_HX8347G_Custom117 NOP ;__Lib_TFT_Defs.mbas,1213 :: else L__TFT_Init_HX8347G_Custom116: ;__Lib_TFT_Defs.mbas,1214 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,1215 :: end if L__TFT_Init_HX8347G_Custom117: ;__Lib_TFT_Defs.mbas,1217 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,1218 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,1220 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,1221 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,1223 :: TFT_Reset_HX8347G() JAL __Lib_TFT_Defs_TFT_Reset_HX8347G+0 NOP ;__Lib_TFT_Defs.mbas,1224 :: TFT_Set_Address_Ptr = @TFT_Set_Address LUI R2, hi_addr(_TFT_Set_Address+0) ORI R2, R2, lo_addr(_TFT_Set_Address+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1225 :: end sub L_end_TFT_Init_HX8347G_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_HX8347G_Custom _TFT_Set_Address_HX8352A: ;__Lib_TFT_Defs.mbas,1234 :: sub procedure TFT_Set_Address_HX8352A(dim x as word y as word) ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1235 :: if (TFT_Disp_Rotation = 90) then SW R25, 4(SP) LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L__TFT_Set_Address_HX8352A525 NOP J L__TFT_Set_Address_HX8352A120 NOP L__TFT_Set_Address_HX8352A525: ;__Lib_TFT_Defs.mbas,1236 :: TFT_Set_Index_Ptr(0x02) SH R26, 8(SP) SH R25, 10(SP) ORI R25, R0, 2 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,1237 :: TFT_Write_Command_Ptr(x >> 8) ANDI R2, R25, 65535 SRL R2, R2, 8 SH R25, 10(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1238 :: TFT_Set_Index_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,1239 :: TFT_Write_Command_Ptr(x) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1240 :: TFT_Set_Index_Ptr(0x06) ORI R25, R0, 6 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,1241 :: TFT_Write_Command_Ptr(y >> 8) ANDI R2, R26, 65535 SRL R2, R2, 8 SH R26, 8(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1242 :: TFT_Set_Index_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,1243 :: TFT_Write_Command_Ptr(y) ANDI R25, R26, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L__TFT_Set_Address_HX8352A121 NOP ;__Lib_TFT_Defs.mbas,1244 :: else L__TFT_Set_Address_HX8352A120: ;__Lib_TFT_Defs.mbas,1245 :: TFT_Set_Index_Ptr(0x02) SH R26, 8(SP) SH R25, 10(SP) ORI R25, R0, 2 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,1246 :: TFT_Write_Command_Ptr(y >> 8) ANDI R2, R26, 65535 SRL R2, R2, 8 SH R26, 8(SP) SH R25, 10(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1247 :: TFT_Set_Index_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,1248 :: TFT_Write_Command_Ptr(y) SH R25, 8(SP) ANDI R25, R26, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1249 :: TFT_Set_Index_Ptr(0x06) ORI R25, R0, 6 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 8(SP) ;__Lib_TFT_Defs.mbas,1250 :: TFT_Write_Command_Ptr(x >> 8) ANDI R2, R25, 65535 SRL R2, R2, 8 SH R25, 8(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1251 :: TFT_Set_Index_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 8(SP) ;__Lib_TFT_Defs.mbas,1252 :: TFT_Write_Command_Ptr(x) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1253 :: end if L__TFT_Set_Address_HX8352A121: ;__Lib_TFT_Defs.mbas,1254 :: TFT_Set_Index_Ptr(0x22) ORI R25, R0, 34 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1255 :: end sub L_end_TFT_Set_Address_HX8352A: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_Set_Address_HX8352A __Lib_TFT_Defs_TFT_Reset_HX8352A: ;__Lib_TFT_Defs.mbas,1262 :: dim _counter as byte ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1264 :: TFT_RST = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,1266 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1269 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,1271 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1274 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,1276 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1278 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1279 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1280 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,1281 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,1284 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,1285 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,1286 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,1287 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,1289 :: TFT_CS = 0 _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,1291 :: TFT_Set_Index_Ptr(0x83) TFT_Write_Command_Ptr(0x02) ORI R25, R0, 131 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1292 :: TFT_Set_Index_Ptr(0x85) TFT_Write_Command_Ptr(0x03) ORI R25, R0, 133 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1293 :: TFT_Set_Index_Ptr(0x8B) TFT_Write_Command_Ptr(0x00) ORI R25, R0, 139 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1294 :: TFT_Set_Index_Ptr(0x8C) TFT_Write_Command_Ptr(0x13) ORI R25, R0, 140 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1295 :: TFT_Set_Index_Ptr(0x91) TFT_Write_Command_Ptr(0x01) ORI R25, R0, 145 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1296 :: TFT_Set_Index_Ptr(0x83) TFT_Write_Command_Ptr(0x00) ORI R25, R0, 131 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1297 :: Delay_10ms() JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1300 :: TFT_Set_Index_Ptr(0x3E) TFT_Write_Command_Ptr(0xC4) ORI R25, R0, 62 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 196 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1301 :: TFT_Set_Index_Ptr(0x3F) TFT_Write_Command_Ptr(0x44) ORI R25, R0, 63 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 68 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1302 :: TFT_Set_Index_Ptr(0x40) TFT_Write_Command_Ptr(0x22) ORI R25, R0, 64 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 34 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1303 :: TFT_Set_Index_Ptr(0x41) TFT_Write_Command_Ptr(0x57) ORI R25, R0, 65 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 87 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1304 :: TFT_Set_Index_Ptr(0x42) TFT_Write_Command_Ptr(0x03) ORI R25, R0, 66 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1305 :: TFT_Set_Index_Ptr(0x43) TFT_Write_Command_Ptr(0x47) ORI R25, R0, 67 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 71 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1306 :: TFT_Set_Index_Ptr(0x44) TFT_Write_Command_Ptr(0x02) ORI R25, R0, 68 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1307 :: TFT_Set_Index_Ptr(0x45) TFT_Write_Command_Ptr(0x55) ORI R25, R0, 69 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 85 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1308 :: TFT_Set_Index_Ptr(0x46) TFT_Write_Command_Ptr(0x06) ORI R25, R0, 70 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1309 :: TFT_Set_Index_Ptr(0x47) TFT_Write_Command_Ptr(0x4C) ORI R25, R0, 71 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 76 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1310 :: TFT_Set_Index_Ptr(0x48) TFT_Write_Command_Ptr(0x06) ORI R25, R0, 72 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1311 :: TFT_Set_Index_Ptr(0x49) TFT_Write_Command_Ptr(0x8C) ORI R25, R0, 73 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 140 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1313 :: TFT_Set_Index_Ptr(0x17) TFT_Write_Command_Ptr(0x91) ORI R25, R0, 23 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 145 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1314 :: TFT_Set_Index_Ptr(0x23) TFT_Write_Command_Ptr(0x01) ORI R25, R0, 35 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1315 :: TFT_Set_Index_Ptr(0x2B) TFT_Write_Command_Ptr(0xF9) ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 249 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1316 :: Delay_10ms() Delay_10ms() JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1317 :: TFT_Set_Index_Ptr(0x18) TFT_Write_Command_Ptr(0x3A) ORI R25, R0, 24 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 58 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1318 :: TFT_Set_Index_Ptr(0x1B) TFT_Write_Command_Ptr(0x11) ORI R25, R0, 27 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 17 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1320 :: TFT_Set_Index_Ptr(0x83) TFT_Write_Command_Ptr(0x02) ORI R25, R0, 131 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1321 :: TFT_Set_Index_Ptr(0x8A) TFT_Write_Command_Ptr(0x06) ORI R25, R0, 138 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1322 :: TFT_Set_Index_Ptr(0x83) TFT_Write_Command_Ptr(0x00) ORI R25, R0, 131 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1323 :: TFT_Set_Index_Ptr(0x1A) TFT_Write_Command_Ptr(0x11) ORI R25, R0, 26 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 17 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1324 :: TFT_Set_Index_Ptr(0x1C) TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 28 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1325 :: TFT_Set_Index_Ptr(0x1F) TFT_Write_Command_Ptr(0x58) ORI R25, R0, 31 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 88 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1326 :: Delay_10ms() Delay_10ms() Delay_10ms() JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1327 :: TFT_Set_Index_Ptr(0x19) TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 25 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1328 :: TFT_Set_Index_Ptr(0x19) TFT_Write_Command_Ptr(0x1A) ORI R25, R0, 25 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 26 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1329 :: Delay_10ms() Delay_10ms() Delay_10ms() Delay_10ms() Delay_10ms() JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1330 :: TFT_Set_Index_Ptr(0x19) TFT_Write_Command_Ptr(0x12) ORI R25, R0, 25 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 18 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1331 :: Delay_10ms() Delay_10ms() Delay_10ms() Delay_10ms() Delay_10ms() JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1332 :: TFT_Set_Index_Ptr(0x1E) TFT_Write_Command_Ptr(0x2E) ORI R25, R0, 30 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 46 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1333 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,1335 :: TFT_Set_Index_Ptr(0x5A) TFT_Write_Command_Ptr(0x01) ORI R25, R0, 90 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1337 :: TFT_Set_Index_Ptr(0x5C) ORI R25, R0, 92 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1338 :: for _counter = 0 to 3 SB R0, 8(SP) L___Lib_TFT_Defs_TFT_Reset_HX8352A124: ;__Lib_TFT_Defs.mbas,1339 :: TFT_Write_Command_Ptr(0x00)'---------0 MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1340 :: TFT_Write_Command_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1341 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1342 :: TFT_Write_Command_Ptr(0x0F) ORI R25, R0, 15 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1343 :: TFT_Write_Command_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1344 :: TFT_Write_Command_Ptr(0x16)'---------5 ORI R25, R0, 22 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1345 :: TFT_Write_Command_Ptr(0x19) ORI R25, R0, 25 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1346 :: TFT_Write_Command_Ptr(0x1C) ORI R25, R0, 28 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1347 :: TFT_Write_Command_Ptr(0x1E) ORI R25, R0, 30 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1348 :: TFT_Write_Command_Ptr(0x1F) ORI R25, R0, 31 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1349 :: TFT_Write_Command_Ptr(0x25)'---------10 ORI R25, R0, 37 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1350 :: TFT_Write_Command_Ptr(0x2A) ORI R25, R0, 42 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1351 :: TFT_Write_Command_Ptr(0x30) ORI R25, R0, 48 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1352 :: TFT_Write_Command_Ptr(0x35) ORI R25, R0, 53 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1353 :: TFT_Write_Command_Ptr(0x39) ORI R25, R0, 57 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1354 :: TFT_Write_Command_Ptr(0x3D)'---------15 ORI R25, R0, 61 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1355 :: TFT_Write_Command_Ptr(0x41) ORI R25, R0, 65 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1356 :: TFT_Write_Command_Ptr(0x45) ORI R25, R0, 69 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1357 :: TFT_Write_Command_Ptr(0x48) ORI R25, R0, 72 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1358 :: TFT_Write_Command_Ptr(0x4C) ORI R25, R0, 76 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1359 :: TFT_Write_Command_Ptr(0x4F)'---------20 ORI R25, R0, 79 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1360 :: TFT_Write_Command_Ptr(0x53) ORI R25, R0, 83 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1361 :: TFT_Write_Command_Ptr(0x58) ORI R25, R0, 88 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1362 :: TFT_Write_Command_Ptr(0x5D) ORI R25, R0, 93 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1363 :: TFT_Write_Command_Ptr(0x61) ORI R25, R0, 97 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1364 :: TFT_Write_Command_Ptr(0x66)'---------25 ORI R25, R0, 102 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1365 :: TFT_Write_Command_Ptr(0x6A) ORI R25, R0, 106 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1366 :: TFT_Write_Command_Ptr(0x6E) ORI R25, R0, 110 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1367 :: TFT_Write_Command_Ptr(0x72) ORI R25, R0, 114 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1368 :: TFT_Write_Command_Ptr(0x76) ORI R25, R0, 118 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1370 :: TFT_Write_Command_Ptr(0x7A)'---------30 ORI R25, R0, 122 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1371 :: TFT_Write_Command_Ptr(0x7E) ORI R25, R0, 126 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1372 :: TFT_Write_Command_Ptr(0x82) ORI R25, R0, 130 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1373 :: TFT_Write_Command_Ptr(0x85) ORI R25, R0, 133 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1374 :: TFT_Write_Command_Ptr(0x89) ORI R25, R0, 137 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1375 :: TFT_Write_Command_Ptr(0x8D)'---------35 ORI R25, R0, 141 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1376 :: TFT_Write_Command_Ptr(0x90) ORI R25, R0, 144 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1377 :: TFT_Write_Command_Ptr(0x94) ORI R25, R0, 148 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1378 :: TFT_Write_Command_Ptr(0x96) ORI R25, R0, 150 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1379 :: TFT_Write_Command_Ptr(0x9A) ORI R25, R0, 154 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1380 :: TFT_Write_Command_Ptr(0x9D)'---------40 ORI R25, R0, 157 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1381 :: TFT_Write_Command_Ptr(0xA1) ORI R25, R0, 161 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1382 :: TFT_Write_Command_Ptr(0xA4) ORI R25, R0, 164 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1383 :: TFT_Write_Command_Ptr(0xA8) ORI R25, R0, 168 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1384 :: TFT_Write_Command_Ptr(0xAB) ORI R25, R0, 171 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1385 :: TFT_Write_Command_Ptr(0xAF)'---------45 ORI R25, R0, 175 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1386 :: TFT_Write_Command_Ptr(0xB3) ORI R25, R0, 179 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1387 :: TFT_Write_Command_Ptr(0xB7) ORI R25, R0, 183 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1388 :: TFT_Write_Command_Ptr(0xBB) ORI R25, R0, 187 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1389 :: TFT_Write_Command_Ptr(0xBF) ORI R25, R0, 191 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1390 :: TFT_Write_Command_Ptr(0xC3)'---------50 ORI R25, R0, 195 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1391 :: TFT_Write_Command_Ptr(0xC8) ORI R25, R0, 200 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1392 :: TFT_Write_Command_Ptr(0xCC) ORI R25, R0, 204 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1393 :: TFT_Write_Command_Ptr(0xD1) ORI R25, R0, 209 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1394 :: TFT_Write_Command_Ptr(0xD6) ORI R25, R0, 214 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1395 :: TFT_Write_Command_Ptr(0xDB)'---------55 ORI R25, R0, 219 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1396 :: TFT_Write_Command_Ptr(0xDE) ORI R25, R0, 222 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1397 :: TFT_Write_Command_Ptr(0xE1) ORI R25, R0, 225 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1398 :: TFT_Write_Command_Ptr(0xE5) ORI R25, R0, 229 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1399 :: TFT_Write_Command_Ptr(0xE7) ORI R25, R0, 231 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1400 :: TFT_Write_Command_Ptr(0xEC)'---------60 ORI R25, R0, 236 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1401 :: TFT_Write_Command_Ptr(0xEF) ORI R25, R0, 239 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1402 :: TFT_Write_Command_Ptr(0xF4) ORI R25, R0, 244 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1403 :: TFT_Write_Command_Ptr(0xFF)'---------63 ORI R25, R0, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1404 :: next _counter LBU R3, 8(SP) ORI R2, R0, 3 BNE R3, R2, L___Lib_TFT_Defs_TFT_Reset_HX8352A528 NOP J L___Lib_TFT_Defs_TFT_Reset_HX8352A127 NOP L___Lib_TFT_Defs_TFT_Reset_HX8352A528: LBU R2, 8(SP) ADDIU R2, R2, 1 SB R2, 8(SP) J L___Lib_TFT_Defs_TFT_Reset_HX8352A124 NOP L___Lib_TFT_Defs_TFT_Reset_HX8352A127: ;__Lib_TFT_Defs.mbas,1406 :: TFT_Set_Index_Ptr(0x3C) TFT_Write_Command_Ptr(0xC0) ORI R25, R0, 60 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 192 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1407 :: TFT_Set_Index_Ptr(0x3D) TFT_Write_Command_Ptr(0x1C) ORI R25, R0, 61 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 28 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1408 :: TFT_Set_Index_Ptr(0x34) TFT_Write_Command_Ptr(0x38) ORI R25, R0, 52 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 56 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1409 :: TFT_Set_Index_Ptr(0x35) TFT_Write_Command_Ptr(0x38) ORI R25, R0, 53 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 56 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1410 :: TFT_Set_Index_Ptr(0x24) TFT_Write_Command_Ptr(0x38) ORI R25, R0, 36 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 56 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1411 :: Delay_10ms() Delay_10ms() Delay_10ms() Delay_10ms() Delay_10ms() JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1412 :: TFT_Set_Index_Ptr(0x24) TFT_Write_Command_Ptr(0x3C) ORI R25, R0, 36 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 60 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1414 :: TFT_Set_Index_Ptr(0x16) ORI R25, R0, 22 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1415 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_HX8352A529 NOP J L___Lib_TFT_Defs_TFT_Reset_HX8352A129 NOP L___Lib_TFT_Defs_TFT_Reset_HX8352A529: ;__Lib_TFT_Defs.mbas,1416 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_HX8352A530 NOP J L___Lib_TFT_Defs_TFT_Reset_HX8352A132 NOP L___Lib_TFT_Defs_TFT_Reset_HX8352A530: ;__Lib_TFT_Defs.mbas,1417 :: TFT_Write_Command_Ptr(0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_HX8352A133 NOP ;__Lib_TFT_Defs.mbas,1418 :: else L___Lib_TFT_Defs_TFT_Reset_HX8352A132: ;__Lib_TFT_Defs.mbas,1419 :: TFT_Write_Command_Ptr(0xC8) ORI R25, R0, 200 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1420 :: end if L___Lib_TFT_Defs_TFT_Reset_HX8352A133: J L___Lib_TFT_Defs_TFT_Reset_HX8352A130 NOP ;__Lib_TFT_Defs.mbas,1421 :: else L___Lib_TFT_Defs_TFT_Reset_HX8352A129: ;__Lib_TFT_Defs.mbas,1422 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_HX8352A531 NOP J L___Lib_TFT_Defs_TFT_Reset_HX8352A135 NOP L___Lib_TFT_Defs_TFT_Reset_HX8352A531: ;__Lib_TFT_Defs.mbas,1423 :: TFT_Write_Command_Ptr(0xD8) ORI R25, R0, 216 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_HX8352A136 NOP ;__Lib_TFT_Defs.mbas,1424 :: else L___Lib_TFT_Defs_TFT_Reset_HX8352A135: ;__Lib_TFT_Defs.mbas,1425 :: TFT_Write_Command_Ptr(0x18) ORI R25, R0, 24 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1426 :: end if L___Lib_TFT_Defs_TFT_Reset_HX8352A136: ;__Lib_TFT_Defs.mbas,1427 :: end if L___Lib_TFT_Defs_TFT_Reset_HX8352A130: ;__Lib_TFT_Defs.mbas,1429 :: TFT_Set_Index_Ptr(0x01) TFT_Write_Command_Ptr(0x06) ORI R25, R0, 1 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1430 :: TFT_Set_Index_Ptr(0x55) TFT_Write_Command_Ptr(0x00) ORI R25, R0, 85 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1434 :: TFT_Set_Index_Ptr(0x02) TFT_Write_Command_Ptr(0x00) ORI R25, R0, 2 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1435 :: TFT_Set_Index_Ptr(0x03) TFT_Write_Command_Ptr(0x00) ORI R25, R0, 3 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1436 :: TFT_Set_Index_Ptr(0x04) TFT_Write_Command_Ptr((240-1) >> 8) ' TFT_DISP_WIDTH ORI R25, R0, 4 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1437 :: TFT_Set_Index_Ptr(0x05) TFT_Write_Command_Ptr(240-1) ' TFT_DISP_WIDTH ORI R25, R0, 5 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 239 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1438 :: TFT_Set_Index_Ptr(0x06) TFT_Write_Command_Ptr(0x00) ORI R25, R0, 6 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1439 :: TFT_Set_Index_Ptr(0x07) TFT_Write_Command_Ptr(0x00) ORI R25, R0, 7 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1440 :: TFT_Set_Index_Ptr(0x08) TFT_Write_Command_Ptr((400-1) >> 8) ' TFT_DISP_HEIGHT ORI R25, R0, 8 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1441 :: TFT_Set_Index_Ptr(0x09) TFT_Write_Command_Ptr(byte(400-1)) ' TFT_DISP_HEIGHT ORI R25, R0, 9 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 143 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1443 :: TFT_Set_Index_Ptr(0x22) ORI R25, R0, 34 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1444 :: Delay_10ms() JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1445 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,1446 :: end sub L_end_TFT_Reset_HX8352A: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of __Lib_TFT_Defs_TFT_Reset_HX8352A _TFT_Init_HX8352A: ;__Lib_TFT_Defs.mbas,1453 :: sub procedure TFT_Init_HX8352A(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1454 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,1455 :: TFT_Set_HX8352A() JAL _TFT_Set_HX8352A+0 NOP ;__Lib_TFT_Defs.mbas,1456 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_HX8352A534 NOP J L__TFT_Init_HX8352A139 NOP L__TFT_Init_HX8352A534: ;__Lib_TFT_Defs.mbas,1457 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1458 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1459 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_HX8352A139: ;__Lib_TFT_Defs.mbas,1462 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,1463 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,1464 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_HX8352A535 NOP J L__TFT_Init_HX8352A142 NOP L__TFT_Init_HX8352A535: ;__Lib_TFT_Defs.mbas,1465 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_HX8352A143 NOP ;__Lib_TFT_Defs.mbas,1466 :: else L__TFT_Init_HX8352A142: ;__Lib_TFT_Defs.mbas,1467 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,1468 :: end if L__TFT_Init_HX8352A143: ;__Lib_TFT_Defs.mbas,1470 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,1471 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,1473 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,1474 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,1475 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,1477 :: TFT_Reset_HX8352A() JAL __Lib_TFT_Defs_TFT_Reset_HX8352A+0 NOP ;__Lib_TFT_Defs.mbas,1478 :: TFT_Set_Address_Ptr = @TFT_Set_Address_HX8352A LUI R2, hi_addr(_TFT_Set_Address_HX8352A+0) ORI R2, R2, lo_addr(_TFT_Set_Address_HX8352A+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1479 :: end sub L_end_TFT_Init_HX8352A: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_HX8352A _TFT_Init_HX8352A_Custom: ;__Lib_TFT_Defs.mbas,1489 :: sub procedure TFT_Init_HX8352A_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1490 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,1491 :: TFT_Set_HX8352A() JAL _TFT_Set_HX8352A+0 NOP ;__Lib_TFT_Defs.mbas,1492 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_HX8352A_Custom538 NOP J L__TFT_Init_HX8352A_Custom146 NOP L__TFT_Init_HX8352A_Custom538: ;__Lib_TFT_Defs.mbas,1493 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1494 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1495 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_HX8352A_Custom146: ;__Lib_TFT_Defs.mbas,1498 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,1499 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,1500 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_HX8352A_Custom539 NOP J L__TFT_Init_HX8352A_Custom149 NOP L__TFT_Init_HX8352A_Custom539: ;__Lib_TFT_Defs.mbas,1501 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_HX8352A_Custom150 NOP ;__Lib_TFT_Defs.mbas,1502 :: else L__TFT_Init_HX8352A_Custom149: ;__Lib_TFT_Defs.mbas,1503 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,1504 :: end if L__TFT_Init_HX8352A_Custom150: ;__Lib_TFT_Defs.mbas,1506 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,1507 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,1509 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,1510 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,1512 :: TFT_Reset_HX8352A() JAL __Lib_TFT_Defs_TFT_Reset_HX8352A+0 NOP ;__Lib_TFT_Defs.mbas,1513 :: TFT_Set_Address_Ptr = @TFT_Set_Address_HX8352A LUI R2, hi_addr(_TFT_Set_Address_HX8352A+0) ORI R2, R2, lo_addr(_TFT_Set_Address_HX8352A+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1514 :: end sub L_end_TFT_Init_HX8352A_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_HX8352A_Custom _TFT_Set_Address_ILI9340: ;__Lib_TFT_Defs.mbas,1523 :: sub procedure TFT_Set_Address_ILI9340(dim x as word y as word) ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1524 :: TFT_Set_Index_Ptr(0x2A) SW R25, 4(SP) SH R26, 8(SP) SH R25, 10(SP) ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,1525 :: TFT_Write_Command_Ptr(x >> 8) ANDI R2, R25, 65535 SRL R2, R2, 8 SH R25, 10(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,1526 :: TFT_Write_Command_Ptr(x) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1527 :: TFT_Set_Index_Ptr(0x2B) ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,1528 :: TFT_Write_Command_Ptr(y >> 8) ANDI R2, R26, 65535 SRL R2, R2, 8 SH R26, 8(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,1529 :: TFT_Write_Command_Ptr(y) ANDI R25, R26, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1530 :: TFT_Set_Index_Ptr(0x2C) ORI R25, R0, 44 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1531 :: end sub L_end_TFT_Set_Address_ILI9340: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_Set_Address_ILI9340 __Lib_TFT_Defs_TFT_Reset_ILI9340: ;__Lib_TFT_Defs.mbas,1537 :: sub procedure TFT_Reset_ILI9340() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1539 :: TFT_RST = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,1541 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1544 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,1546 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1549 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,1551 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1553 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1554 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1555 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,1556 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,1558 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,1559 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,1560 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,1561 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,1563 :: TFT_CS = 0 _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,1565 :: TFT_Set_Index_Ptr(0x11)'Exit Sleep ORI R25, R0, 17 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1566 :: Delay_10ms() Delay_10ms() Delay_10ms() JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1567 :: Delay_10ms() Delay_10ms() Delay_10ms() JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1569 :: TFT_Set_Index_Ptr(0xCB)TFT_Write_Command_Ptr(0x01)'AP[2:0] ORI R25, R0, 203 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1571 :: TFT_Set_Index_Ptr(0xC0)TFT_Write_Command_Ptr(0x26) 'VRH[5:0] ORI R25, R0, 192 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 38 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1572 :: TFT_Write_Command_Ptr(0x04)'VC[2:0] ORI R25, R0, 4 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1574 :: TFT_Set_Index_Ptr(0xC1)TFT_Write_Command_Ptr(0x04) 'SAP[2:0]BT[3:0] ORI R25, R0, 193 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 4 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1577 :: TFT_Set_Index_Ptr(0xC5)TFT_Write_Command_Ptr(0x34) 'VCM control ORI R25, R0, 197 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 52 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1578 :: TFT_Write_Command_Ptr(0x40) ORI R25, R0, 64 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1579 :: TFT_Set_Index_Ptr(0x36) ' memory access control ORI R25, R0, 54 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1580 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ILI9340542 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9340154 NOP L___Lib_TFT_Defs_TFT_Reset_ILI9340542: ;__Lib_TFT_Defs.mbas,1581 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ILI9340543 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9340157 NOP L___Lib_TFT_Defs_TFT_Reset_ILI9340543: ;__Lib_TFT_Defs.mbas,1582 :: TFT_Write_Command_Ptr (0xC8) ORI R25, R0, 200 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9340158 NOP ;__Lib_TFT_Defs.mbas,1583 :: else L___Lib_TFT_Defs_TFT_Reset_ILI9340157: ;__Lib_TFT_Defs.mbas,1584 :: TFT_Write_Command_Ptr (0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1585 :: end if L___Lib_TFT_Defs_TFT_Reset_ILI9340158: J L___Lib_TFT_Defs_TFT_Reset_ILI9340155 NOP ;__Lib_TFT_Defs.mbas,1586 :: else L___Lib_TFT_Defs_TFT_Reset_ILI9340154: ;__Lib_TFT_Defs.mbas,1587 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ILI9340544 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9340160 NOP L___Lib_TFT_Defs_TFT_Reset_ILI9340544: ;__Lib_TFT_Defs.mbas,1588 :: TFT_Write_Command_Ptr (0xA8) ORI R25, R0, 168 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9340161 NOP ;__Lib_TFT_Defs.mbas,1589 :: else L___Lib_TFT_Defs_TFT_Reset_ILI9340160: ;__Lib_TFT_Defs.mbas,1590 :: TFT_Write_Command_Ptr (0x68) ORI R25, R0, 104 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1591 :: end if L___Lib_TFT_Defs_TFT_Reset_ILI9340161: ;__Lib_TFT_Defs.mbas,1592 :: end if L___Lib_TFT_Defs_TFT_Reset_ILI9340155: ;__Lib_TFT_Defs.mbas,1594 :: TFT_Set_Index_Ptr(0xB1)TFT_Write_Command_Ptr(0x00) ' Frame Rate Control ORI R25, R0, 177 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1595 :: TFT_Write_Command_Ptr(0x18) ORI R25, R0, 24 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1597 :: TFT_Set_Index_Ptr(0xB6)TFT_Write_Command_Ptr(0x0A) ' Display Function Control ORI R25, R0, 182 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1598 :: TFT_Write_Command_Ptr(0xA2) ORI R25, R0, 162 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1600 :: TFT_Set_Index_Ptr(0xC7)TFT_Write_Command_Ptr(0xCD) 'VCOM Control , VMF[6:0] ORI R25, R0, 199 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 205 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1602 :: TFT_Set_Index_Ptr(0xE8) ORI R25, R0, 232 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1603 :: TFT_Write_Command_Ptr(0x89) ORI R25, R0, 137 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1604 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1605 :: TFT_Write_Command_Ptr(0x79) ORI R25, R0, 121 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1607 :: TFT_Set_Index_Ptr(0xF2)TFT_Write_Command_Ptr(0x00) ' 3Gamma Function Disable ORI R25, R0, 242 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1609 :: TFT_Set_Index_Ptr(0xE0)TFT_Write_Command_Ptr(0x0F) ORI R25, R0, 224 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ORI R25, R0, 15 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1610 :: TFT_Write_Command_Ptr(0x1D) ORI R25, R0, 29 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1611 :: TFT_Write_Command_Ptr(0x1A) ORI R25, R0, 26 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1612 :: TFT_Write_Command_Ptr(0x0B) ORI R25, R0, 11 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1613 :: TFT_Write_Command_Ptr(0x0F) ORI R25, R0, 15 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1614 :: TFT_Write_Command_Ptr(0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1615 :: TFT_Write_Command_Ptr(0x47) ORI R25, R0, 71 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1616 :: TFT_Write_Command_Ptr(0xD6) ORI R25, R0, 214 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1617 :: TFT_Write_Command_Ptr(0x37) ORI R25, R0, 55 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1618 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1619 :: TFT_Write_Command_Ptr(0x0C) ORI R25, R0, 12 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1620 :: TFT_Write_Command_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1621 :: TFT_Write_Command_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1622 :: TFT_Write_Command_Ptr(0x05) ORI R25, R0, 5 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1623 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1625 :: TFT_Set_Index_Ptr(0xE1)TFT_Write_Command_Ptr(0x00) ORI R25, R0, 225 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1626 :: TFT_Write_Command_Ptr(0x22) ORI R25, R0, 34 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1627 :: TFT_Write_Command_Ptr(0x25) ORI R25, R0, 37 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1628 :: TFT_Write_Command_Ptr(0x04) ORI R25, R0, 4 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1629 :: TFT_Write_Command_Ptr(0x10) ORI R25, R0, 16 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1630 :: TFT_Write_Command_Ptr(0x06) ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1631 :: TFT_Write_Command_Ptr(0x38) ORI R25, R0, 56 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1632 :: TFT_Write_Command_Ptr(0x7F) ORI R25, R0, 127 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1633 :: TFT_Write_Command_Ptr(0x48) ORI R25, R0, 72 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1634 :: TFT_Write_Command_Ptr(0x05) ORI R25, R0, 5 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1635 :: TFT_Write_Command_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1636 :: TFT_Write_Command_Ptr(0x38) ORI R25, R0, 56 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1637 :: TFT_Write_Command_Ptr(0x38) ORI R25, R0, 56 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1638 :: TFT_Write_Command_Ptr(0x3A) ORI R25, R0, 58 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1639 :: TFT_Write_Command_Ptr(0x0F) ORI R25, R0, 15 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1641 :: TFT_Set_Index_Ptr(0x29) ORI R25, R0, 41 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1642 :: TFT_Set_Index_Ptr(0x3A) ORI R25, R0, 58 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1643 :: TFT_Write_Command_Ptr(0x05) ORI R25, R0, 5 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1647 :: TFT_Set_Index_Ptr(0x2A) ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1648 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1649 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1650 :: TFT_Write_Command_Ptr((TFT_DISP_WIDTH-1) >> 8) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) ADDIU R2, R2, -1 ANDI R2, R2, 65535 SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1651 :: TFT_Write_Command_Ptr(TFT_DISP_WIDTH-1) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) ADDIU R2, R2, -1 ANDI R25, R2, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1652 :: TFT_Set_Index_Ptr(0x2B) ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1653 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1654 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1655 :: TFT_Write_Command_Ptr((TFT_DISP_HEIGHT-1) >> 8) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) ADDIU R2, R2, -1 ANDI R2, R2, 65535 SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1656 :: TFT_Write_Command_Ptr(TFT_DISP_HEIGHT-1) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) ADDIU R2, R2, -1 ANDI R25, R2, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1658 :: Delay_10ms() JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1659 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,1660 :: end sub L_end_TFT_Reset_ILI9340: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of __Lib_TFT_Defs_TFT_Reset_ILI9340 _TFT_Init_ILI9340: ;__Lib_TFT_Defs.mbas,1667 :: sub procedure TFT_Init_ILI9340(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1668 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,1669 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9340547 NOP J L__TFT_Init_ILI9340164 NOP L__TFT_Init_ILI9340547: ;__Lib_TFT_Defs.mbas,1670 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1671 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1672 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9340164: ;__Lib_TFT_Defs.mbas,1675 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,1676 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,1677 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9340548 NOP J L__TFT_Init_ILI9340167 NOP L__TFT_Init_ILI9340548: ;__Lib_TFT_Defs.mbas,1678 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9340168 NOP ;__Lib_TFT_Defs.mbas,1679 :: else L__TFT_Init_ILI9340167: ;__Lib_TFT_Defs.mbas,1680 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,1681 :: end if L__TFT_Init_ILI9340168: ;__Lib_TFT_Defs.mbas,1683 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,1684 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,1686 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,1687 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,1688 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,1690 :: TFT_Reset_ILI9340() JAL __Lib_TFT_Defs_TFT_Reset_ILI9340+0 NOP ;__Lib_TFT_Defs.mbas,1691 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9340 LUI R2, hi_addr(_TFT_Set_Address_ILI9340+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9340+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1692 :: end sub L_end_TFT_Init_ILI9340: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9340 _TFT_Init_ILI9340_Custom: ;__Lib_TFT_Defs.mbas,1702 :: sub procedure TFT_Init_ILI9340_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1703 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,1704 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9340_Custom551 NOP J L__TFT_Init_ILI9340_Custom171 NOP L__TFT_Init_ILI9340_Custom551: ;__Lib_TFT_Defs.mbas,1705 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1706 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1707 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9340_Custom171: ;__Lib_TFT_Defs.mbas,1710 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,1711 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,1712 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9340_Custom552 NOP J L__TFT_Init_ILI9340_Custom174 NOP L__TFT_Init_ILI9340_Custom552: ;__Lib_TFT_Defs.mbas,1713 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9340_Custom175 NOP ;__Lib_TFT_Defs.mbas,1714 :: else L__TFT_Init_ILI9340_Custom174: ;__Lib_TFT_Defs.mbas,1715 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,1716 :: end if L__TFT_Init_ILI9340_Custom175: ;__Lib_TFT_Defs.mbas,1718 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,1719 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,1721 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,1722 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,1724 :: TFT_Reset_ILI9340() JAL __Lib_TFT_Defs_TFT_Reset_ILI9340+0 NOP ;__Lib_TFT_Defs.mbas,1725 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9340 LUI R2, hi_addr(_TFT_Set_Address_ILI9340+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9340+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1726 :: end sub L_end_TFT_Init_ILI9340_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9340_Custom _TFT_Init_ILI9340_8bit: ;__Lib_TFT_Defs.mbas,1735 :: sub procedure TFT_Init_ILI9340_8bit(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1736 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,1737 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9340_8bit555 NOP J L__TFT_Init_ILI9340_8bit178 NOP L__TFT_Init_ILI9340_8bit555: ;__Lib_TFT_Defs.mbas,1738 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1739 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1740 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9340_8bit178: ;__Lib_TFT_Defs.mbas,1743 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,1744 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,1745 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9340_8bit556 NOP J L__TFT_Init_ILI9340_8bit181 NOP L__TFT_Init_ILI9340_8bit556: ;__Lib_TFT_Defs.mbas,1746 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9340_8bit182 NOP ;__Lib_TFT_Defs.mbas,1747 :: else L__TFT_Init_ILI9340_8bit181: ;__Lib_TFT_Defs.mbas,1748 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,1749 :: end if L__TFT_Init_ILI9340_8bit182: ;__Lib_TFT_Defs.mbas,1751 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,1752 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,1754 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,1755 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,1756 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,1758 :: TFT_Reset_ILI9340() JAL __Lib_TFT_Defs_TFT_Reset_ILI9340+0 NOP ;__Lib_TFT_Defs.mbas,1759 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9340 LUI R2, hi_addr(_TFT_Set_Address_ILI9340+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9340+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1760 :: end sub L_end_TFT_Init_ILI9340_8bit: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9340_8bit _TFT_Init_ILI9340_8bit_Custom: ;__Lib_TFT_Defs.mbas,1770 :: sub procedure TFT_Init_ILI9340_8bit_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1771 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,1772 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9340_8bit_Custom559 NOP J L__TFT_Init_ILI9340_8bit_Custom185 NOP L__TFT_Init_ILI9340_8bit_Custom559: ;__Lib_TFT_Defs.mbas,1773 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1774 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1775 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9340_8bit_Custom185: ;__Lib_TFT_Defs.mbas,1778 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,1779 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,1780 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9340_8bit_Custom560 NOP J L__TFT_Init_ILI9340_8bit_Custom188 NOP L__TFT_Init_ILI9340_8bit_Custom560: ;__Lib_TFT_Defs.mbas,1781 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9340_8bit_Custom189 NOP ;__Lib_TFT_Defs.mbas,1782 :: else L__TFT_Init_ILI9340_8bit_Custom188: ;__Lib_TFT_Defs.mbas,1783 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,1784 :: end if L__TFT_Init_ILI9340_8bit_Custom189: ;__Lib_TFT_Defs.mbas,1786 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,1787 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,1789 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,1790 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,1792 :: TFT_Reset_ILI9340() JAL __Lib_TFT_Defs_TFT_Reset_ILI9340+0 NOP ;__Lib_TFT_Defs.mbas,1793 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9340 LUI R2, hi_addr(_TFT_Set_Address_ILI9340+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9340+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1794 :: end sub L_end_TFT_Init_ILI9340_8bit_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9340_8bit_Custom __Lib_TFT_Defs_TFT_Reset_ST7789V: ;__Lib_TFT_Defs.mbas,1802 :: sub procedure TFT_Reset_ST7789V() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1804 :: TFT_RST = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,1806 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1809 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,1811 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1814 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,1816 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1818 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1819 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,1820 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,1821 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,1823 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,1824 :: Delay_10ms() JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1825 :: TFT_RST = 0 _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,1826 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,1827 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,1828 :: Delay_100ms() Delay_10ms() Delay_10ms() JAL _Delay_100ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1829 :: TFT_CS = 0 _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,1831 :: TFT_Set_Index_Ptr(0x11) ORI R25, R0, 17 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1832 :: Delay_100ms() 'Delay 120ms JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,1833 :: Delay_10ms() Delay_10ms() JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,1835 :: TFT_Set_Index_Ptr(0x36) ORI R25, R0, 54 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1836 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1838 :: TFT_Set_Index_Ptr(0x3a) ORI R25, R0, 58 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1839 :: TFT_Write_Command_Ptr(0x05) '65k ORI R25, R0, 5 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1841 :: TFT_Set_Index_Ptr(0xb2) ORI R25, R0, 178 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1842 :: TFT_Write_Command_Ptr(0x0c) ORI R25, R0, 12 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1843 :: TFT_Write_Command_Ptr(0x0c) ORI R25, R0, 12 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1844 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1845 :: TFT_Write_Command_Ptr(0x33) ORI R25, R0, 51 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1846 :: TFT_Write_Command_Ptr(0x33) ORI R25, R0, 51 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1848 :: TFT_Set_Index_Ptr(0xb7) ORI R25, R0, 183 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1849 :: TFT_Write_Command_Ptr(0x70) ORI R25, R0, 112 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1852 :: TFT_Set_Index_Ptr(0xbb) ORI R25, R0, 187 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1853 :: TFT_Write_Command_Ptr(0x1B)'VCOM ORI R25, R0, 27 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1855 :: TFT_Set_Index_Ptr(0xc0) ORI R25, R0, 192 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1856 :: TFT_Write_Command_Ptr(0x2c) ORI R25, R0, 44 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1858 :: TFT_Set_Index_Ptr(0xc2) ORI R25, R0, 194 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1859 :: TFT_Write_Command_Ptr(0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1861 :: TFT_Set_Index_Ptr(0xc3) ORI R25, R0, 195 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1862 :: TFT_Write_Command_Ptr(0x0B) ORI R25, R0, 11 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1864 :: TFT_Set_Index_Ptr(0xc4) ORI R25, R0, 196 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1865 :: TFT_Write_Command_Ptr(0x27) ORI R25, R0, 39 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1867 :: TFT_Set_Index_Ptr(0xc6) ORI R25, R0, 198 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1868 :: TFT_Write_Command_Ptr(0x0f) ORI R25, R0, 15 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1870 :: TFT_Set_Index_Ptr(0xd0) ORI R25, R0, 208 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1871 :: TFT_Write_Command_Ptr(0xa4) ORI R25, R0, 164 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1872 :: TFT_Write_Command_Ptr(0xA1) ORI R25, R0, 161 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1874 :: TFT_Set_Index_Ptr(0xe0) ORI R25, R0, 224 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1875 :: TFT_Write_Command_Ptr(0xD0) ORI R25, R0, 208 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1876 :: TFT_Write_Command_Ptr(0x06) ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1877 :: TFT_Write_Command_Ptr(0x0B) ORI R25, R0, 11 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1878 :: TFT_Write_Command_Ptr(0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1879 :: TFT_Write_Command_Ptr(0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1880 :: TFT_Write_Command_Ptr(0x30) ORI R25, R0, 48 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1881 :: TFT_Write_Command_Ptr(0x30) ORI R25, R0, 48 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1882 :: TFT_Write_Command_Ptr(0x5B) ORI R25, R0, 91 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1883 :: TFT_Write_Command_Ptr(0x4B) ORI R25, R0, 75 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1884 :: TFT_Write_Command_Ptr(0x18) ORI R25, R0, 24 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1885 :: TFT_Write_Command_Ptr(0x14) ORI R25, R0, 20 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1886 :: TFT_Write_Command_Ptr(0x14) ORI R25, R0, 20 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1887 :: TFT_Write_Command_Ptr(0x2C) ORI R25, R0, 44 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1888 :: TFT_Write_Command_Ptr(0x32) ORI R25, R0, 50 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1890 :: TFT_Set_Index_Ptr(0xe1) ORI R25, R0, 225 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1891 :: TFT_Write_Command_Ptr(0xD0) ORI R25, R0, 208 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1892 :: TFT_Write_Command_Ptr(0x05) ORI R25, R0, 5 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1893 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1894 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1895 :: TFT_Write_Command_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1896 :: TFT_Write_Command_Ptr(0x28) ORI R25, R0, 40 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1897 :: TFT_Write_Command_Ptr(0x32) ORI R25, R0, 50 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1898 :: TFT_Write_Command_Ptr(0x2C) ORI R25, R0, 44 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1899 :: TFT_Write_Command_Ptr(0x49) ORI R25, R0, 73 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1900 :: TFT_Write_Command_Ptr(0x18) ORI R25, R0, 24 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1901 :: TFT_Write_Command_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1902 :: TFT_Write_Command_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1903 :: TFT_Write_Command_Ptr(0x2C) ORI R25, R0, 44 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1904 :: TFT_Write_Command_Ptr(0x33) ORI R25, R0, 51 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1906 :: TFT_Set_Index_Ptr(0x21) '·´ÏÔ ORI R25, R0, 33 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1908 :: TFT_Set_Index_Ptr(0x2A) ' Column Address Set ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1909 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1910 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1911 :: TFT_Write_Command_Ptr(TFT_DISP_WIDTH >> 8) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1912 :: TFT_Write_Command_Ptr(TFT_DISP_WIDTH) LHU R25, Offset(_TFT_DISP_WIDTH+0)(GP) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1913 :: TFT_Set_Index_Ptr(0x2B) 'Row Address Set ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1914 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1915 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1916 :: TFT_Write_Command_Ptr(TFT_DISP_HEIGHT >> 8) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1917 :: TFT_Write_Command_Ptr(TFT_DISP_HEIGHT) LHU R25, Offset(_TFT_DISP_HEIGHT+0)(GP) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1919 :: TFT_Set_Index_Ptr(0x36) ' memory access control ORI R25, R0, 54 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1920 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ST7789V562 NOP J L___Lib_TFT_Defs_TFT_Reset_ST7789V192 NOP L___Lib_TFT_Defs_TFT_Reset_ST7789V562: ;__Lib_TFT_Defs.mbas,1921 :: if (Is_TFT_Rotated_180()) then JAL _Is_TFT_Rotated_180+0 NOP BNE R2, R0, L___Lib_TFT_Defs_TFT_Reset_ST7789V564 NOP J L___Lib_TFT_Defs_TFT_Reset_ST7789V195 NOP L___Lib_TFT_Defs_TFT_Reset_ST7789V564: ;__Lib_TFT_Defs.mbas,1922 :: TFT_Write_Command_Ptr (0xC0) ORI R25, R0, 192 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_ST7789V196 NOP ;__Lib_TFT_Defs.mbas,1923 :: else L___Lib_TFT_Defs_TFT_Reset_ST7789V195: ;__Lib_TFT_Defs.mbas,1924 :: TFT_Write_Command_Ptr (0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1925 :: end if L___Lib_TFT_Defs_TFT_Reset_ST7789V196: J L___Lib_TFT_Defs_TFT_Reset_ST7789V193 NOP ;__Lib_TFT_Defs.mbas,1926 :: else L___Lib_TFT_Defs_TFT_Reset_ST7789V192: ;__Lib_TFT_Defs.mbas,1927 :: if (Is_TFT_Rotated_180()) then JAL _Is_TFT_Rotated_180+0 NOP BNE R2, R0, L___Lib_TFT_Defs_TFT_Reset_ST7789V566 NOP J L___Lib_TFT_Defs_TFT_Reset_ST7789V198 NOP L___Lib_TFT_Defs_TFT_Reset_ST7789V566: ;__Lib_TFT_Defs.mbas,1928 :: TFT_Write_Command_Ptr (0xA0) ORI R25, R0, 160 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_ST7789V199 NOP ;__Lib_TFT_Defs.mbas,1929 :: else L___Lib_TFT_Defs_TFT_Reset_ST7789V198: ;__Lib_TFT_Defs.mbas,1930 :: TFT_Write_Command_Ptr (0x60) ORI R25, R0, 96 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1931 :: end if L___Lib_TFT_Defs_TFT_Reset_ST7789V199: ;__Lib_TFT_Defs.mbas,1932 :: end if L___Lib_TFT_Defs_TFT_Reset_ST7789V193: ;__Lib_TFT_Defs.mbas,1934 :: TFT_Set_Index_Ptr(0x29) 'display on ORI R25, R0, 41 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1935 :: TFT_Set_Index_Ptr(0x2c) ORI R25, R0, 44 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,1936 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,1937 :: end sub L_end_TFT_Reset_ST7789V: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of __Lib_TFT_Defs_TFT_Reset_ST7789V _TFT_Init_ST7789V_8bit_Custom: ;__Lib_TFT_Defs.mbas,1944 :: sub procedure TFT_Init_ST7789V_8bit_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1945 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,1946 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ST7789V_8bit_Custom569 NOP J L__TFT_Init_ST7789V_8bit_Custom202 NOP L__TFT_Init_ST7789V_8bit_Custom569: ;__Lib_TFT_Defs.mbas,1947 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1948 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1949 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ST7789V_8bit_Custom202: ;__Lib_TFT_Defs.mbas,1952 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,1953 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,1954 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ST7789V_8bit_Custom570 NOP J L__TFT_Init_ST7789V_8bit_Custom205 NOP L__TFT_Init_ST7789V_8bit_Custom570: ;__Lib_TFT_Defs.mbas,1955 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ST7789V_8bit_Custom206 NOP ;__Lib_TFT_Defs.mbas,1956 :: else L__TFT_Init_ST7789V_8bit_Custom205: ;__Lib_TFT_Defs.mbas,1957 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,1958 :: end if L__TFT_Init_ST7789V_8bit_Custom206: ;__Lib_TFT_Defs.mbas,1960 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,1961 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,1963 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,1964 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,1966 :: TFT_Reset_ST7789V() JAL __Lib_TFT_Defs_TFT_Reset_ST7789V+0 NOP ;__Lib_TFT_Defs.mbas,1967 :: TFT_Set_Address_Ptr = @TFT_Set_Address_SST7715R LUI R2, hi_addr(_TFT_Set_Address_SST7715R+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SST7715R+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1968 :: end sub L_end_TFT_Init_ST7789V_8bit_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ST7789V_8bit_Custom _TFT_Init_ST7789V_8bit: ;__Lib_TFT_Defs.mbas,1975 :: sub procedure TFT_Init_ST7789V_8bit(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,1976 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,1977 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ST7789V_8bit573 NOP J L__TFT_Init_ST7789V_8bit209 NOP L__TFT_Init_ST7789V_8bit573: ;__Lib_TFT_Defs.mbas,1978 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1979 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,1980 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ST7789V_8bit209: ;__Lib_TFT_Defs.mbas,1983 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,1984 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,1985 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ST7789V_8bit574 NOP J L__TFT_Init_ST7789V_8bit212 NOP L__TFT_Init_ST7789V_8bit574: ;__Lib_TFT_Defs.mbas,1986 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ST7789V_8bit213 NOP ;__Lib_TFT_Defs.mbas,1987 :: else L__TFT_Init_ST7789V_8bit212: ;__Lib_TFT_Defs.mbas,1988 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,1989 :: end if L__TFT_Init_ST7789V_8bit213: ;__Lib_TFT_Defs.mbas,1991 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,1992 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,1994 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,1995 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,1996 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,1998 :: TFT_Reset_ST7789V() JAL __Lib_TFT_Defs_TFT_Reset_ST7789V+0 NOP ;__Lib_TFT_Defs.mbas,1999 :: TFT_Set_Address_Ptr = @TFT_Set_Address_SST7715R LUI R2, hi_addr(_TFT_Set_Address_SST7715R+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SST7715R+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2000 :: end sub L_end_TFT_Init_ST7789V_8bit: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ST7789V_8bit _TFT_Init_ST7789V_16bit_Custom: ;__Lib_TFT_Defs.mbas,2007 :: sub procedure TFT_Init_ST7789V_16bit_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2008 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,2009 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ST7789V_16bit_Custom577 NOP J L__TFT_Init_ST7789V_16bit_Custom216 NOP L__TFT_Init_ST7789V_16bit_Custom577: ;__Lib_TFT_Defs.mbas,2010 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2011 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2012 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ST7789V_16bit_Custom216: ;__Lib_TFT_Defs.mbas,2015 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,2016 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,2017 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ST7789V_16bit_Custom578 NOP J L__TFT_Init_ST7789V_16bit_Custom219 NOP L__TFT_Init_ST7789V_16bit_Custom578: ;__Lib_TFT_Defs.mbas,2018 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ST7789V_16bit_Custom220 NOP ;__Lib_TFT_Defs.mbas,2019 :: else L__TFT_Init_ST7789V_16bit_Custom219: ;__Lib_TFT_Defs.mbas,2020 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,2021 :: end if L__TFT_Init_ST7789V_16bit_Custom220: ;__Lib_TFT_Defs.mbas,2023 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,2024 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,2026 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,2027 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,2029 :: TFT_Reset_ST7789V() JAL __Lib_TFT_Defs_TFT_Reset_ST7789V+0 NOP ;__Lib_TFT_Defs.mbas,2030 :: TFT_Set_Address_Ptr = @TFT_Set_Address_SST7715R LUI R2, hi_addr(_TFT_Set_Address_SST7715R+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SST7715R+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2031 :: end sub L_end_TFT_Init_ST7789V_16bit_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ST7789V_16bit_Custom _TFT_Init_ST7789V_16bit: ;__Lib_TFT_Defs.mbas,2038 :: sub procedure TFT_Init_ST7789V_16bit(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2039 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,2040 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ST7789V_16bit581 NOP J L__TFT_Init_ST7789V_16bit223 NOP L__TFT_Init_ST7789V_16bit581: ;__Lib_TFT_Defs.mbas,2041 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2042 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2043 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ST7789V_16bit223: ;__Lib_TFT_Defs.mbas,2046 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,2047 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,2048 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ST7789V_16bit582 NOP J L__TFT_Init_ST7789V_16bit226 NOP L__TFT_Init_ST7789V_16bit582: ;__Lib_TFT_Defs.mbas,2049 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ST7789V_16bit227 NOP ;__Lib_TFT_Defs.mbas,2050 :: else L__TFT_Init_ST7789V_16bit226: ;__Lib_TFT_Defs.mbas,2051 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,2052 :: end if L__TFT_Init_ST7789V_16bit227: ;__Lib_TFT_Defs.mbas,2054 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,2055 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,2057 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,2058 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,2059 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,2061 :: TFT_Reset_ST7789V() JAL __Lib_TFT_Defs_TFT_Reset_ST7789V+0 NOP ;__Lib_TFT_Defs.mbas,2062 :: TFT_Set_Address_Ptr = @TFT_Set_Address_SST7715R LUI R2, hi_addr(_TFT_Set_Address_SST7715R+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SST7715R+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2063 :: end sub L_end_TFT_Init_ST7789V_16bit: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ST7789V_16bit __Lib_TFT_Defs_TFT_ReadId_ST7789V_or_ILI9341: ;__Lib_TFT_Defs.mbas,2067 :: dim id as longword ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2068 :: id = 0 SW R25, 4(SP) SW R0, 8(SP) ;__Lib_TFT_Defs.mbas,2071 :: TFT_RST = 0 _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,2073 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2076 :: TFT_RS = 0 _LX INS R2, R0, BitPos(TFT_RS+0), 1 _SX ;__Lib_TFT_Defs.mbas,2078 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2081 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,2083 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2085 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2086 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2087 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,2088 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,2090 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,2091 :: Delay_ms(100) LUI R24, 20 ORI R24, R24, 22612 L___Lib_TFT_Defs_TFT_ReadId_ST7789V_or_ILI9341229: ADDIU R24, R24, -1 BNE R24, R0, L___Lib_TFT_Defs_TFT_ReadId_ST7789V_or_ILI9341229 NOP NOP NOP ;__Lib_TFT_Defs.mbas,2093 :: TFT_CS = 0 _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,2095 :: TFT_Set_Index_Ptr(0x04) ORI R25, R0, 4 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2098 :: TFT_Set_DataPort_Direction_Input() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction_Input+0 NOP ;__Lib_TFT_Defs.mbas,2099 :: Read_From_Port() ' don't care JAL __Lib_TFT_Defs_Read_From_Port+0 NOP ;__Lib_TFT_Defs.mbas,2100 :: id = id or longword(Read_From_Port() and 0x00FF) << 8 JAL __Lib_TFT_Defs_Read_From_Port+0 NOP ANDI R2, R2, 255 ANDI R2, R2, 65535 SLL R3, R2, 8 LW R2, 8(SP) OR R2, R2, R3 SW R2, 8(SP) ;__Lib_TFT_Defs.mbas,2101 :: id = id or longword(Read_From_Port() and 0x00FF) << 16 JAL __Lib_TFT_Defs_Read_From_Port+0 NOP ANDI R2, R2, 255 ANDI R2, R2, 65535 SLL R3, R2, 16 LW R2, 8(SP) OR R2, R2, R3 SW R2, 8(SP) ;__Lib_TFT_Defs.mbas,2102 :: id = id or longword(Read_From_Port() and 0x00FF) << 24 JAL __Lib_TFT_Defs_Read_From_Port+0 NOP ANDI R2, R2, 255 ANDI R2, R2, 65535 SLL R3, R2, 24 LW R2, 8(SP) OR R2, R2, R3 SW R2, 8(SP) ;__Lib_TFT_Defs.mbas,2103 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,2105 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,2107 :: Result = id ; Result start address is: 8 (R2) LW R2, 8(SP) ;__Lib_TFT_Defs.mbas,2108 :: end sub ; Result end address is: 8 (R2) L_end_TFT_ReadId_ST7789V_or_ILI9341: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of __Lib_TFT_Defs_TFT_ReadId_ST7789V_or_ILI9341 __Lib_TFT_Defs_TFT_Reset_ILI9341: ;__Lib_TFT_Defs.mbas,2118 :: sub procedure TFT_Reset_ILI9341() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2120 :: TFT_RST = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,2122 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2125 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,2127 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2130 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,2132 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2134 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2135 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2136 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,2137 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,2139 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2140 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,2141 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2142 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2144 :: TFT_CS = 0 _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,2145 :: TFT_Set_Index_Ptr(0x01) ' software reset ORI R25, R0, 1 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2146 :: Delay_5ms() JAL _Delay_5ms+0 NOP ;__Lib_TFT_Defs.mbas,2147 :: TFT_Set_Index_Ptr(0x28) ' display off ORI R25, R0, 40 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2149 :: TFT_Set_Index_Ptr(0xcf) ORI R25, R0, 207 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2150 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2151 :: TFT_Write_Command_Ptr(0x83) ORI R25, R0, 131 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2152 :: TFT_Write_Command_Ptr(0x30) ORI R25, R0, 48 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2154 :: TFT_Set_Index_Ptr(0xed) ORI R25, R0, 237 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2155 :: TFT_Write_Command_Ptr(0x64) ORI R25, R0, 100 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2156 :: TFT_Write_Command_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2157 :: TFT_Write_Command_Ptr(0x12) ORI R25, R0, 18 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2158 :: TFT_Write_Command_Ptr(0x81) ORI R25, R0, 129 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2160 :: TFT_Set_Index_Ptr(0xe8) ORI R25, R0, 232 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2161 :: TFT_Write_Command_Ptr(0x85) ORI R25, R0, 133 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2162 :: TFT_Write_Command_Ptr(0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2163 :: TFT_Write_Command_Ptr(0x79) ORI R25, R0, 121 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2165 :: TFT_Set_Index_Ptr(0xcb) ORI R25, R0, 203 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2166 :: TFT_Write_Command_Ptr(0x39) ORI R25, R0, 57 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2167 :: TFT_Write_Command_Ptr(0x2c) ORI R25, R0, 44 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2168 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2169 :: TFT_Write_Command_Ptr(0x34) ORI R25, R0, 52 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2170 :: TFT_Write_Command_Ptr(0x02) ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2172 :: TFT_Set_Index_Ptr(0xf7) ORI R25, R0, 247 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2173 :: TFT_Write_Command_Ptr(0x20) ORI R25, R0, 32 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2175 :: TFT_Set_Index_Ptr(0xea) ORI R25, R0, 234 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2176 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2177 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2179 :: TFT_Set_Index_Ptr(0xc0) ' power control ORI R25, R0, 192 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2180 :: TFT_Write_Command_Ptr(0x26) ORI R25, R0, 38 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2182 :: TFT_Set_Index_Ptr(0xc1) ' power control ORI R25, R0, 193 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2183 :: TFT_Write_Command_Ptr(0x11) ORI R25, R0, 17 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2185 :: TFT_Set_Index_Ptr(0xc5) ' vcom control ORI R25, R0, 197 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2186 :: TFT_Write_Command_Ptr(0x35) ORI R25, R0, 53 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2187 :: TFT_Write_Command_Ptr(0x3e) ORI R25, R0, 62 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2189 :: TFT_Set_Index_Ptr(0xc7) ' vcom control ORI R25, R0, 199 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2190 :: TFT_Write_Command_Ptr(0xbe) ORI R25, R0, 190 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2192 :: TFT_Set_Index_Ptr(0x36) ' memory access control ORI R25, R0, 54 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2193 :: if (TFT_DISP_ROTATION = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ILI9341585 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9341233 NOP L___Lib_TFT_Defs_TFT_Reset_ILI9341585: ;__Lib_TFT_Defs.mbas,2194 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ILI9341586 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9341236 NOP L___Lib_TFT_Defs_TFT_Reset_ILI9341586: ;__Lib_TFT_Defs.mbas,2195 :: TFT_Write_Command_Ptr (0x88) ORI R25, R0, 136 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9341237 NOP ;__Lib_TFT_Defs.mbas,2196 :: else L___Lib_TFT_Defs_TFT_Reset_ILI9341236: ;__Lib_TFT_Defs.mbas,2197 :: TFT_Write_Command_Ptr (0x48) ORI R25, R0, 72 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2198 :: end if L___Lib_TFT_Defs_TFT_Reset_ILI9341237: J L___Lib_TFT_Defs_TFT_Reset_ILI9341234 NOP ;__Lib_TFT_Defs.mbas,2199 :: else L___Lib_TFT_Defs_TFT_Reset_ILI9341233: ;__Lib_TFT_Defs.mbas,2200 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ILI9341587 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9341239 NOP L___Lib_TFT_Defs_TFT_Reset_ILI9341587: ;__Lib_TFT_Defs.mbas,2201 :: TFT_Write_Command_Ptr (0xE8) ORI R25, R0, 232 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9341240 NOP ;__Lib_TFT_Defs.mbas,2202 :: else L___Lib_TFT_Defs_TFT_Reset_ILI9341239: ;__Lib_TFT_Defs.mbas,2203 :: TFT_Write_Command_Ptr (0x28) ORI R25, R0, 40 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2204 :: end if L___Lib_TFT_Defs_TFT_Reset_ILI9341240: ;__Lib_TFT_Defs.mbas,2205 :: end if L___Lib_TFT_Defs_TFT_Reset_ILI9341234: ;__Lib_TFT_Defs.mbas,2207 :: TFT_Set_Index_Ptr(0x3A) ' pixel format set ORI R25, R0, 58 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2208 :: TFT_Write_Command_Ptr(0x55) ' 16bit/pixel ORI R25, R0, 85 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2210 :: TFT_Set_Index_Ptr(0xB1) ' frame rate ORI R25, R0, 177 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2211 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2212 :: TFT_Write_Command_Ptr(0x1B) ' 70 ORI R25, R0, 27 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2215 :: TFT_Set_Index_Ptr(0xf2) ' 3Gamma Function Disable ORI R25, R0, 242 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2216 :: TFT_Write_Command_Ptr(0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2218 :: TFT_Set_Index_Ptr(0x26) ORI R25, R0, 38 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2219 :: TFT_Write_Command_Ptr(0x01) ' gamma set 4 gamma curve 01/02/04/08 ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2221 :: TFT_Set_Index_Ptr(0xE0) ' positive gamma correction ORI R25, R0, 224 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2222 :: TFT_Write_Command_Ptr(0x1f) ORI R25, R0, 31 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2223 :: TFT_Write_Command_Ptr(0x1a) ORI R25, R0, 26 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2224 :: TFT_Write_Command_Ptr(0x18) ORI R25, R0, 24 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2225 :: TFT_Write_Command_Ptr(0x0a) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2226 :: TFT_Write_Command_Ptr(0x0f) ORI R25, R0, 15 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2227 :: TFT_Write_Command_Ptr(0x06) ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2228 :: TFT_Write_Command_Ptr(0x45) ORI R25, R0, 69 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2229 :: TFT_Write_Command_Ptr(0x87) ORI R25, R0, 135 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2230 :: TFT_Write_Command_Ptr(0x32) ORI R25, R0, 50 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2231 :: TFT_Write_Command_Ptr(0x0a) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2232 :: TFT_Write_Command_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2233 :: TFT_Write_Command_Ptr(0x02) ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2234 :: TFT_Write_Command_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2235 :: TFT_Write_Command_Ptr(0x05) ORI R25, R0, 5 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2236 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2238 :: TFT_Set_Index_Ptr(0xE1) ' negamma correction ORI R25, R0, 225 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2239 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2240 :: TFT_Write_Command_Ptr(0x25) ORI R25, R0, 37 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2241 :: TFT_Write_Command_Ptr(0x27) ORI R25, R0, 39 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2242 :: TFT_Write_Command_Ptr(0x05) ORI R25, R0, 5 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2243 :: TFT_Write_Command_Ptr(0x10) ORI R25, R0, 16 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2244 :: TFT_Write_Command_Ptr(0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2245 :: TFT_Write_Command_Ptr(0x3a) ORI R25, R0, 58 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2246 :: TFT_Write_Command_Ptr(0x78) ORI R25, R0, 120 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2247 :: TFT_Write_Command_Ptr(0x4d) ORI R25, R0, 77 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2248 :: TFT_Write_Command_Ptr(0x05) ORI R25, R0, 5 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2249 :: TFT_Write_Command_Ptr(0x18) ORI R25, R0, 24 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2250 :: TFT_Write_Command_Ptr(0x0d) ORI R25, R0, 13 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2251 :: TFT_Write_Command_Ptr(0x38) ORI R25, R0, 56 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2252 :: TFT_Write_Command_Ptr(0x3a) ORI R25, R0, 58 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2253 :: TFT_Write_Command_Ptr(0x1f) ORI R25, R0, 31 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2257 :: TFT_Set_Index_Ptr(0x2A) ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2258 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2259 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2260 :: TFT_Write_Command_Ptr((TFT_DISP_WIDTH - 1) >> 8) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) ADDIU R2, R2, -1 ANDI R2, R2, 65535 SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2261 :: TFT_Write_Command_Ptr(TFT_DISP_WIDTH-1) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) ADDIU R2, R2, -1 ANDI R25, R2, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2263 :: TFT_Set_Index_Ptr(0x2B) ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2264 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2265 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2266 :: TFT_Write_Command_Ptr((TFT_DISP_HEIGHT - 1) >> 8) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) ADDIU R2, R2, -1 ANDI R2, R2, 65535 SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2267 :: TFT_Write_Command_Ptr(TFT_DISP_HEIGHT-1) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) ADDIU R2, R2, -1 ANDI R25, R2, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2269 :: TFT_Set_Index_Ptr(0xb7) ' entry mode set ORI R25, R0, 183 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2270 :: TFT_Write_Command_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2272 :: TFT_Set_Index_Ptr(0xb6) ' display function control ORI R25, R0, 182 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2273 :: TFT_Write_Command_Ptr(0x0a) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2274 :: TFT_Write_Command_Ptr(0x82) ORI R25, R0, 130 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2275 :: TFT_Write_Command_Ptr(0x27) ORI R25, R0, 39 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2276 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2278 :: TFT_Set_Index_Ptr(0x11) ' sleep out ORI R25, R0, 17 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2279 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2280 :: TFT_Set_Index_Ptr(0x29) ' display on ORI R25, R0, 41 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2281 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2282 :: TFT_Set_Index_Ptr(0x2c) ' memory write ORI R25, R0, 44 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2283 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,2284 :: end sub L_end_TFT_Reset_ILI9341: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of __Lib_TFT_Defs_TFT_Reset_ILI9341 _TFT_Init_ILI9341_16bit: ;__Lib_TFT_Defs.mbas,2291 :: sub procedure TFT_Init_ILI9341_16bit(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2292 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,2293 :: if(Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9341_16bit590 NOP J L__TFT_Init_ILI9341_16bit243 NOP L__TFT_Init_ILI9341_16bit590: ;__Lib_TFT_Defs.mbas,2294 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2295 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2296 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9341_16bit243: ;__Lib_TFT_Defs.mbas,2299 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,2300 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,2301 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9341_16bit591 NOP J L__TFT_Init_ILI9341_16bit246 NOP L__TFT_Init_ILI9341_16bit591: ;__Lib_TFT_Defs.mbas,2302 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9341_16bit247 NOP ;__Lib_TFT_Defs.mbas,2303 :: else L__TFT_Init_ILI9341_16bit246: ;__Lib_TFT_Defs.mbas,2304 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,2305 :: end if L__TFT_Init_ILI9341_16bit247: ;__Lib_TFT_Defs.mbas,2307 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,2308 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,2310 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,2311 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,2312 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,2314 :: if (TFT_ReadId_ST7789V_or_ILI9341() = TFT_ST7789_HW_ID) then JAL __Lib_TFT_Defs_TFT_ReadId_ST7789V_or_ILI9341+0 NOP LUI R3, 21125 ORI R3, R3, 34048 BEQ R2, R3, L__TFT_Init_ILI9341_16bit592 NOP J L__TFT_Init_ILI9341_16bit249 NOP L__TFT_Init_ILI9341_16bit592: ;__Lib_TFT_Defs.mbas,2316 :: TFT_Reset_ST7789V() JAL __Lib_TFT_Defs_TFT_Reset_ST7789V+0 NOP ;__Lib_TFT_Defs.mbas,2317 :: TFT_Set_Address_Ptr = @TFT_Set_Address_SST7715R LUI R2, hi_addr(_TFT_Set_Address_SST7715R+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SST7715R+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) J L__TFT_Init_ILI9341_16bit250 NOP ;__Lib_TFT_Defs.mbas,2318 :: else L__TFT_Init_ILI9341_16bit249: ;__Lib_TFT_Defs.mbas,2320 :: TFT_Reset_ILI9341() JAL __Lib_TFT_Defs_TFT_Reset_ILI9341+0 NOP ;__Lib_TFT_Defs.mbas,2321 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9340 LUI R2, hi_addr(_TFT_Set_Address_ILI9340+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9340+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2322 :: end if L__TFT_Init_ILI9341_16bit250: ;__Lib_TFT_Defs.mbas,2328 :: end sub L_end_TFT_Init_ILI9341_16bit: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9341_16bit _TFT_Init_ILI9341_16bit_Custom: ;__Lib_TFT_Defs.mbas,2338 :: sub procedure TFT_Init_ILI9341_16bit_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2339 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,2340 :: if(Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9341_16bit_Custom595 NOP J L__TFT_Init_ILI9341_16bit_Custom253 NOP L__TFT_Init_ILI9341_16bit_Custom595: ;__Lib_TFT_Defs.mbas,2341 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2342 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2343 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9341_16bit_Custom253: ;__Lib_TFT_Defs.mbas,2346 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,2347 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,2348 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9341_16bit_Custom596 NOP J L__TFT_Init_ILI9341_16bit_Custom256 NOP L__TFT_Init_ILI9341_16bit_Custom596: ;__Lib_TFT_Defs.mbas,2349 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9341_16bit_Custom257 NOP ;__Lib_TFT_Defs.mbas,2350 :: else L__TFT_Init_ILI9341_16bit_Custom256: ;__Lib_TFT_Defs.mbas,2351 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,2352 :: end if L__TFT_Init_ILI9341_16bit_Custom257: ;__Lib_TFT_Defs.mbas,2354 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,2355 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,2357 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,2358 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,2360 :: if (TFT_ReadId_ST7789V_or_ILI9341() = TFT_ST7789_HW_ID) then JAL __Lib_TFT_Defs_TFT_ReadId_ST7789V_or_ILI9341+0 NOP LUI R3, 21125 ORI R3, R3, 34048 BEQ R2, R3, L__TFT_Init_ILI9341_16bit_Custom597 NOP J L__TFT_Init_ILI9341_16bit_Custom259 NOP L__TFT_Init_ILI9341_16bit_Custom597: ;__Lib_TFT_Defs.mbas,2362 :: TFT_Reset_ST7789V() JAL __Lib_TFT_Defs_TFT_Reset_ST7789V+0 NOP ;__Lib_TFT_Defs.mbas,2363 :: TFT_Set_Address_Ptr = @TFT_Set_Address_SST7715R LUI R2, hi_addr(_TFT_Set_Address_SST7715R+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SST7715R+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) J L__TFT_Init_ILI9341_16bit_Custom260 NOP ;__Lib_TFT_Defs.mbas,2364 :: else L__TFT_Init_ILI9341_16bit_Custom259: ;__Lib_TFT_Defs.mbas,2366 :: TFT_Reset_ILI9341() JAL __Lib_TFT_Defs_TFT_Reset_ILI9341+0 NOP ;__Lib_TFT_Defs.mbas,2367 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9340 LUI R2, hi_addr(_TFT_Set_Address_ILI9340+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9340+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2368 :: end if L__TFT_Init_ILI9341_16bit_Custom260: ;__Lib_TFT_Defs.mbas,2374 :: end sub L_end_TFT_Init_ILI9341_16bit_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9341_16bit_Custom _TFT_Init_ILI9341_8bit: ;__Lib_TFT_Defs.mbas,2383 :: sub procedure TFT_Init_ILI9341_8bit(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2384 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,2385 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9341_8bit600 NOP J L__TFT_Init_ILI9341_8bit263 NOP L__TFT_Init_ILI9341_8bit600: ;__Lib_TFT_Defs.mbas,2386 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2387 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2388 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9341_8bit263: ;__Lib_TFT_Defs.mbas,2391 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,2392 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,2393 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9341_8bit601 NOP J L__TFT_Init_ILI9341_8bit266 NOP L__TFT_Init_ILI9341_8bit601: ;__Lib_TFT_Defs.mbas,2394 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9341_8bit267 NOP ;__Lib_TFT_Defs.mbas,2395 :: else L__TFT_Init_ILI9341_8bit266: ;__Lib_TFT_Defs.mbas,2396 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,2397 :: end if L__TFT_Init_ILI9341_8bit267: ;__Lib_TFT_Defs.mbas,2399 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,2400 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,2402 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,2403 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,2404 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,2406 :: if (TFT_ReadId_ST7789V_or_ILI9341() = TFT_ST7789_HW_ID) then JAL __Lib_TFT_Defs_TFT_ReadId_ST7789V_or_ILI9341+0 NOP LUI R3, 21125 ORI R3, R3, 34048 BEQ R2, R3, L__TFT_Init_ILI9341_8bit602 NOP J L__TFT_Init_ILI9341_8bit269 NOP L__TFT_Init_ILI9341_8bit602: ;__Lib_TFT_Defs.mbas,2408 :: TFT_Reset_ST7789V() JAL __Lib_TFT_Defs_TFT_Reset_ST7789V+0 NOP ;__Lib_TFT_Defs.mbas,2409 :: TFT_Set_Address_Ptr = @TFT_Set_Address_SST7715R LUI R2, hi_addr(_TFT_Set_Address_SST7715R+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SST7715R+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) J L__TFT_Init_ILI9341_8bit270 NOP ;__Lib_TFT_Defs.mbas,2410 :: else L__TFT_Init_ILI9341_8bit269: ;__Lib_TFT_Defs.mbas,2412 :: TFT_Reset_ILI9341() JAL __Lib_TFT_Defs_TFT_Reset_ILI9341+0 NOP ;__Lib_TFT_Defs.mbas,2413 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9340 LUI R2, hi_addr(_TFT_Set_Address_ILI9340+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9340+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2414 :: end if L__TFT_Init_ILI9341_8bit270: ;__Lib_TFT_Defs.mbas,2420 :: end sub L_end_TFT_Init_ILI9341_8bit: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9341_8bit _TFT_Init_ILI9341_8bit_Custom: ;__Lib_TFT_Defs.mbas,2430 :: sub procedure TFT_Init_ILI9341_8bit_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2431 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,2432 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9341_8bit_Custom605 NOP J L__TFT_Init_ILI9341_8bit_Custom273 NOP L__TFT_Init_ILI9341_8bit_Custom605: ;__Lib_TFT_Defs.mbas,2433 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2434 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2435 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9341_8bit_Custom273: ;__Lib_TFT_Defs.mbas,2438 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,2439 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,2440 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9341_8bit_Custom606 NOP J L__TFT_Init_ILI9341_8bit_Custom276 NOP L__TFT_Init_ILI9341_8bit_Custom606: ;__Lib_TFT_Defs.mbas,2441 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9341_8bit_Custom277 NOP ;__Lib_TFT_Defs.mbas,2442 :: else L__TFT_Init_ILI9341_8bit_Custom276: ;__Lib_TFT_Defs.mbas,2443 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,2444 :: end if L__TFT_Init_ILI9341_8bit_Custom277: ;__Lib_TFT_Defs.mbas,2446 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,2447 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,2449 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,2450 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,2452 :: if (TFT_ReadId_ST7789V_or_ILI9341() = TFT_ST7789_HW_ID) then JAL __Lib_TFT_Defs_TFT_ReadId_ST7789V_or_ILI9341+0 NOP LUI R3, 21125 ORI R3, R3, 34048 BEQ R2, R3, L__TFT_Init_ILI9341_8bit_Custom607 NOP J L__TFT_Init_ILI9341_8bit_Custom279 NOP L__TFT_Init_ILI9341_8bit_Custom607: ;__Lib_TFT_Defs.mbas,2454 :: TFT_Reset_ST7789V() JAL __Lib_TFT_Defs_TFT_Reset_ST7789V+0 NOP ;__Lib_TFT_Defs.mbas,2455 :: TFT_Set_Address_Ptr = @TFT_Set_Address_SST7715R LUI R2, hi_addr(_TFT_Set_Address_SST7715R+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SST7715R+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) J L__TFT_Init_ILI9341_8bit_Custom280 NOP ;__Lib_TFT_Defs.mbas,2456 :: else L__TFT_Init_ILI9341_8bit_Custom279: ;__Lib_TFT_Defs.mbas,2458 :: TFT_Reset_ILI9341() JAL __Lib_TFT_Defs_TFT_Reset_ILI9341+0 NOP ;__Lib_TFT_Defs.mbas,2459 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9340 LUI R2, hi_addr(_TFT_Set_Address_ILI9340+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9340+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2460 :: end if L__TFT_Init_ILI9341_8bit_Custom280: ;__Lib_TFT_Defs.mbas,2466 :: end sub L_end_TFT_Init_ILI9341_8bit_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9341_8bit_Custom _TFT_Set_Address_ILI9342: ;__Lib_TFT_Defs.mbas,2476 :: sub procedure TFT_Set_Address_ILI9342(dim x as word y as word) ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2477 :: TFT_Set_Index_Ptr(0x2A) SW R25, 4(SP) SH R26, 8(SP) SH R25, 10(SP) ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,2478 :: TFT_Write_Command_Ptr(x >> 8) ANDI R2, R25, 65535 SRL R2, R2, 8 SH R25, 10(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,2479 :: TFT_Write_Command_Ptr(x) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2480 :: TFT_Set_Index_Ptr(0x2B) ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,2481 :: TFT_Write_Command_Ptr(y >> 8) ANDI R2, R26, 65535 SRL R2, R2, 8 SH R26, 8(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,2482 :: TFT_Write_Command_Ptr(y) ANDI R25, R26, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2483 :: TFT_Set_Index_Ptr(0x2C) ORI R25, R0, 44 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2484 :: end sub L_end_TFT_Set_Address_ILI9342: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_Set_Address_ILI9342 __Lib_TFT_Defs_TFT_Reset_ILI9342: ;__Lib_TFT_Defs.mbas,2490 :: sub procedure TFT_Reset_ILI9342() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2492 :: TFT_RST = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,2494 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2497 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,2499 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2502 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,2504 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2506 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2507 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2508 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,2509 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,2511 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2512 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,2513 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2514 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2516 :: TFT_CS = 0 _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,2517 :: TFT_Set_Index_Ptr(0xB9) ' Set EXTC ORI R25, R0, 185 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2518 :: TFT_Write_Command_Ptr(0xFF) ORI R25, R0, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2519 :: TFT_Write_Command_Ptr(0x93) ORI R25, R0, 147 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2520 :: TFT_Write_Command_Ptr(0x42) ORI R25, R0, 66 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2522 :: TFT_Set_Index_Ptr(0x36) ' memory access control ORI R25, R0, 54 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2523 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ILI9342610 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9342284 NOP L___Lib_TFT_Defs_TFT_Reset_ILI9342610: ;__Lib_TFT_Defs.mbas,2524 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ILI9342611 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9342287 NOP L___Lib_TFT_Defs_TFT_Reset_ILI9342611: ;__Lib_TFT_Defs.mbas,2525 :: TFT_Write_Command_Ptr (0x60) ORI R25, R0, 96 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9342288 NOP ;__Lib_TFT_Defs.mbas,2526 :: else L___Lib_TFT_Defs_TFT_Reset_ILI9342287: ;__Lib_TFT_Defs.mbas,2527 :: TFT_Write_Command_Ptr (0xA0) ORI R25, R0, 160 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2528 :: end if L___Lib_TFT_Defs_TFT_Reset_ILI9342288: J L___Lib_TFT_Defs_TFT_Reset_ILI9342285 NOP ;__Lib_TFT_Defs.mbas,2529 :: else L___Lib_TFT_Defs_TFT_Reset_ILI9342284: ;__Lib_TFT_Defs.mbas,2530 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ILI9342612 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9342290 NOP L___Lib_TFT_Defs_TFT_Reset_ILI9342612: ;__Lib_TFT_Defs.mbas,2531 :: TFT_Write_Command_Ptr (0xC0) ORI R25, R0, 192 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9342291 NOP ;__Lib_TFT_Defs.mbas,2532 :: else L___Lib_TFT_Defs_TFT_Reset_ILI9342290: ;__Lib_TFT_Defs.mbas,2533 :: TFT_Write_Command_Ptr (0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2534 :: end if L___Lib_TFT_Defs_TFT_Reset_ILI9342291: ;__Lib_TFT_Defs.mbas,2535 :: end if L___Lib_TFT_Defs_TFT_Reset_ILI9342285: ;__Lib_TFT_Defs.mbas,2538 :: TFT_Set_Index_Ptr(0x2A) ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2539 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2540 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2541 :: TFT_Write_Command_Ptr(Hi(TFT_DISP_WIDTH)) LBU R25, Offset(_TFT_DISP_WIDTH+1)(GP) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2542 :: TFT_Write_Command_Ptr(TFT_DISP_WIDTH) LHU R25, Offset(_TFT_DISP_WIDTH+0)(GP) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2544 :: TFT_Set_Index_Ptr(0x2B) ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2545 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2546 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2547 :: TFT_Write_Command_Ptr(Hi(TFT_DISP_HEIGHT)) LBU R25, Offset(_TFT_DISP_HEIGHT+1)(GP) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2548 :: TFT_Write_Command_Ptr(TFT_DISP_HEIGHT) LHU R25, Offset(_TFT_DISP_HEIGHT+0)(GP) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2550 :: TFT_Set_Index_Ptr(0x3A) ' pixel format set ORI R25, R0, 58 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2551 :: TFT_Write_Command_Ptr (0x55) ORI R25, R0, 85 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2553 :: TFT_Set_Index_Ptr(0xB1) ' Display Waveform Cycle 1 ORI R25, R0, 177 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2554 :: TFT_Write_Command_Ptr (0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2555 :: TFT_Write_Command_Ptr (0x10) ORI R25, R0, 16 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2557 :: TFT_Set_Index_Ptr(0xB6) ' Display Function Control ORI R25, R0, 182 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2558 :: TFT_Write_Command_Ptr (0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2559 :: TFT_Write_Command_Ptr (0xE2) ORI R25, R0, 226 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2560 :: TFT_Write_Command_Ptr (0x1D) ORI R25, R0, 29 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2562 :: TFT_Set_Index_Ptr(0xC0) ' Power Control 1 ORI R25, R0, 192 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2563 :: TFT_Write_Command_Ptr (0x35) ORI R25, R0, 53 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2564 :: TFT_Write_Command_Ptr (0x0e) ORI R25, R0, 14 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2566 :: TFT_Set_Index_Ptr(0xC1) ' Power Control 2 ORI R25, R0, 193 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2567 :: TFT_Write_Command_Ptr (0x02) ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2569 :: TFT_Set_Index_Ptr(0xC5) ' VCOM Control 1 ORI R25, R0, 197 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2570 :: TFT_Write_Command_Ptr (0x31) ORI R25, R0, 49 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2571 :: TFT_Write_Command_Ptr (0x3C) ORI R25, R0, 60 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2573 :: TFT_Set_Index_Ptr(0xB8) ' Oscillator Control ORI R25, R0, 184 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2574 :: TFT_Write_Command_Ptr (0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2576 :: TFT_Set_Index_Ptr(0x26) ' Gamma Set ORI R25, R0, 38 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2577 :: TFT_Write_Command_Ptr (0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2579 :: TFT_Set_Index_Ptr(0xC7) ' VCOM Control 2 ORI R25, R0, 199 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2580 :: TFT_Write_Command_Ptr (0xBF) ORI R25, R0, 191 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2582 :: TFT_Set_Index_Ptr(0xE0) ' Positive Gamma Correction ORI R25, R0, 224 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2583 :: TFT_Write_Command_Ptr (0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2584 :: TFT_Write_Command_Ptr (0x1C) ORI R25, R0, 28 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2585 :: TFT_Write_Command_Ptr (0x1B) ORI R25, R0, 27 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2586 :: TFT_Write_Command_Ptr (0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2587 :: TFT_Write_Command_Ptr (0x0D) ORI R25, R0, 13 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2588 :: TFT_Write_Command_Ptr (0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2589 :: TFT_Write_Command_Ptr (0x4B) ORI R25, R0, 75 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2590 :: TFT_Write_Command_Ptr (0xB8) ORI R25, R0, 184 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2591 :: TFT_Write_Command_Ptr (0x3B) ORI R25, R0, 59 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2592 :: TFT_Write_Command_Ptr (0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2593 :: TFT_Write_Command_Ptr (0x10) ORI R25, R0, 16 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2594 :: TFT_Write_Command_Ptr (0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2595 :: TFT_Write_Command_Ptr (0x20) ORI R25, R0, 32 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2596 :: TFT_Write_Command_Ptr (0x20) ORI R25, R0, 32 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2597 :: TFT_Write_Command_Ptr (0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2599 :: TFT_Set_Index_Ptr(0xE1) ' Negative Gamma Correction ORI R25, R0, 225 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2600 :: TFT_Write_Command_Ptr (0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2601 :: TFT_Write_Command_Ptr (0x23) ORI R25, R0, 35 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2602 :: TFT_Write_Command_Ptr (0x24) ORI R25, R0, 36 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2603 :: TFT_Write_Command_Ptr (0x06) ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2604 :: TFT_Write_Command_Ptr (0x12) ORI R25, R0, 18 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2605 :: TFT_Write_Command_Ptr (0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2606 :: TFT_Write_Command_Ptr (0x34) ORI R25, R0, 52 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2607 :: TFT_Write_Command_Ptr (0x47) ORI R25, R0, 71 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2608 :: TFT_Write_Command_Ptr (0x44) ORI R25, R0, 68 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2609 :: TFT_Write_Command_Ptr (0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2610 :: TFT_Write_Command_Ptr (0x0F) ORI R25, R0, 15 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2611 :: TFT_Write_Command_Ptr (0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2612 :: TFT_Write_Command_Ptr (0x1F) ORI R25, R0, 31 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2613 :: TFT_Write_Command_Ptr (0x1F) ORI R25, R0, 31 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2614 :: TFT_Write_Command_Ptr (0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2616 :: TFT_Set_Index_Ptr(0x13) ' Set Normal Mode ORI R25, R0, 19 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2618 :: TFT_Set_Index_Ptr(0x11) 'Exit Sleep ORI R25, R0, 17 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2619 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2620 :: TFT_Set_Index_Ptr(0x11) 'Exit Sleep ORI R25, R0, 17 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2621 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2622 :: TFT_Set_Index_Ptr(0x29) ORI R25, R0, 41 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2623 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,2624 :: end sub L_end_TFT_Reset_ILI9342: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of __Lib_TFT_Defs_TFT_Reset_ILI9342 _TFT_Init_ILI9342: ;__Lib_TFT_Defs.mbas,2631 :: sub procedure TFT_Init_ILI9342(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2632 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,2633 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9342615 NOP J L__TFT_Init_ILI9342294 NOP L__TFT_Init_ILI9342615: ;__Lib_TFT_Defs.mbas,2634 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2635 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2636 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9342294: ;__Lib_TFT_Defs.mbas,2639 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,2640 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,2641 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9342616 NOP J L__TFT_Init_ILI9342297 NOP L__TFT_Init_ILI9342616: ;__Lib_TFT_Defs.mbas,2642 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9342298 NOP ;__Lib_TFT_Defs.mbas,2643 :: else L__TFT_Init_ILI9342297: ;__Lib_TFT_Defs.mbas,2644 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,2645 :: end if L__TFT_Init_ILI9342298: ;__Lib_TFT_Defs.mbas,2647 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,2648 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,2650 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,2651 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,2652 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,2654 :: TFT_Reset_ILI9342() JAL __Lib_TFT_Defs_TFT_Reset_ILI9342+0 NOP ;__Lib_TFT_Defs.mbas,2655 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9342 LUI R2, hi_addr(_TFT_Set_Address_ILI9342+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9342+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2656 :: end sub L_end_TFT_Init_ILI9342: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9342 _TFT_Init_ILI9342_Custom: ;__Lib_TFT_Defs.mbas,2666 :: sub procedure TFT_Init_ILI9342_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2667 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,2668 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9342_Custom619 NOP J L__TFT_Init_ILI9342_Custom301 NOP L__TFT_Init_ILI9342_Custom619: ;__Lib_TFT_Defs.mbas,2669 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2670 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2671 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9342_Custom301: ;__Lib_TFT_Defs.mbas,2674 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,2675 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,2676 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9342_Custom620 NOP J L__TFT_Init_ILI9342_Custom304 NOP L__TFT_Init_ILI9342_Custom620: ;__Lib_TFT_Defs.mbas,2677 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9342_Custom305 NOP ;__Lib_TFT_Defs.mbas,2678 :: else L__TFT_Init_ILI9342_Custom304: ;__Lib_TFT_Defs.mbas,2679 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,2680 :: end if L__TFT_Init_ILI9342_Custom305: ;__Lib_TFT_Defs.mbas,2682 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,2683 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,2685 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,2686 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,2688 :: TFT_Reset_ILI9342() JAL __Lib_TFT_Defs_TFT_Reset_ILI9342+0 NOP ;__Lib_TFT_Defs.mbas,2689 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9342 LUI R2, hi_addr(_TFT_Set_Address_ILI9342+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9342+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2690 :: end sub L_end_TFT_Init_ILI9342_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9342_Custom _TFT_Set_Address_ILI9481: ;__Lib_TFT_Defs.mbas,2699 :: sub procedure TFT_Set_Address_ILI9481(dim x as word y as word) ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2700 :: TFT_Set_Index_Ptr(0x2A) SW R25, 4(SP) SH R26, 8(SP) SH R25, 10(SP) ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,2701 :: TFT_Write_Command_Ptr(x >> 8) ANDI R2, R25, 65535 SRL R2, R2, 8 SH R25, 10(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,2702 :: TFT_Write_Command_Ptr(x) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2703 :: TFT_Set_Index_Ptr(0x2B) ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,2704 :: TFT_Write_Command_Ptr(y >> 8) ANDI R2, R26, 65535 SRL R2, R2, 8 SH R26, 8(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,2705 :: TFT_Write_Command_Ptr(y) ANDI R25, R26, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2706 :: TFT_Set_Index_Ptr(0x2C) ORI R25, R0, 44 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2707 :: end sub L_end_TFT_Set_Address_ILI9481: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_Set_Address_ILI9481 __Lib_TFT_Defs_TFT_Reset_ILI9481: ;__Lib_TFT_Defs.mbas,2713 :: sub procedure TFT_Reset_ILI9481() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2715 :: TFT_RST = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,2717 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2720 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,2722 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2725 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,2727 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2729 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2730 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,2731 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,2732 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,2734 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2735 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,2736 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2737 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,2739 :: TFT_CS = 0 _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,2741 :: TFT_Set_Index_Ptr(0x11) ORI R25, R0, 17 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2742 :: Delay_10ms() Delay_10ms() JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,2743 :: TFT_Set_Index_Ptr(0xD0) ORI R25, R0, 208 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2744 :: TFT_Write_Command_Ptr(0x07) ORI R25, R0, 7 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2745 :: TFT_Write_Command_Ptr(0x41) ORI R25, R0, 65 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2746 :: TFT_Write_Command_Ptr(0x1D) ORI R25, R0, 29 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2748 :: TFT_Set_Index_Ptr(0xD1) ORI R25, R0, 209 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2749 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2750 :: TFT_Write_Command_Ptr(0x2F) ORI R25, R0, 47 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2751 :: TFT_Write_Command_Ptr(0x1C) ORI R25, R0, 28 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2753 :: TFT_Set_Index_Ptr(0xD2) ORI R25, R0, 210 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2754 :: TFT_Write_Command_Ptr(0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2755 :: TFT_Write_Command_Ptr(0x11) ORI R25, R0, 17 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2757 :: TFT_Set_Index_Ptr(0xC0) ORI R25, R0, 192 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2758 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2759 :: TFT_Write_Command_Ptr(0x3B) ORI R25, R0, 59 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2760 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2761 :: TFT_Write_Command_Ptr(0x02) ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2762 :: TFT_Write_Command_Ptr(0x11) ORI R25, R0, 17 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2764 :: TFT_Set_Index_Ptr(0xC5) ' Frame rate ORI R25, R0, 197 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2765 :: TFT_Write_Command_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2767 :: TFT_Set_Index_Ptr(0xC8) ' Gamma Setting ORI R25, R0, 200 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2768 :: TFT_Write_Command_Ptr(0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2769 :: TFT_Write_Command_Ptr(0x47) ORI R25, R0, 71 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2770 :: TFT_Write_Command_Ptr(0x33) ORI R25, R0, 51 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2771 :: TFT_Write_Command_Ptr(0x23) ORI R25, R0, 35 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2772 :: TFT_Write_Command_Ptr(0x04) ORI R25, R0, 4 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2773 :: TFT_Write_Command_Ptr(0x0C) ORI R25, R0, 12 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2774 :: TFT_Write_Command_Ptr(0x44) ORI R25, R0, 68 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2775 :: TFT_Write_Command_Ptr(0x03) ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2776 :: TFT_Write_Command_Ptr(0x67) ORI R25, R0, 103 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2777 :: TFT_Write_Command_Ptr(0x32) ORI R25, R0, 50 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2778 :: TFT_Write_Command_Ptr(0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2779 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2781 :: TFT_Set_Index_Ptr(0xE4) ORI R25, R0, 228 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2782 :: TFT_Write_Command_Ptr(0xA0) ORI R25, R0, 160 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2784 :: TFT_Set_Index_Ptr(0xF0) ORI R25, R0, 240 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2785 :: TFT_Write_Command_Ptr(0x08) ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2787 :: TFT_Set_Index_Ptr(0xF3) ORI R25, R0, 243 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2788 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2789 :: TFT_Write_Command_Ptr(0x1A) ORI R25, R0, 26 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2791 :: TFT_Set_Index_Ptr(0xF7) ORI R25, R0, 247 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2792 :: TFT_Write_Command_Ptr(0x80) ORI R25, R0, 128 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2794 :: TFT_Set_Index_Ptr(0x13) ' Set Normal Mode ORI R25, R0, 19 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2796 :: TFT_Set_Index_Ptr(0x38) ' Exit Idle Mode ORI R25, R0, 56 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2798 :: TFT_Set_Index_Ptr(0x36) ' memory access control ORI R25, R0, 54 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2799 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ILI9481623 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9481309 NOP L___Lib_TFT_Defs_TFT_Reset_ILI9481623: ;__Lib_TFT_Defs.mbas,2800 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ILI9481624 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9481312 NOP L___Lib_TFT_Defs_TFT_Reset_ILI9481624: ;__Lib_TFT_Defs.mbas,2801 :: TFT_Write_Command_Ptr (0x09) ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9481313 NOP ;__Lib_TFT_Defs.mbas,2802 :: else L___Lib_TFT_Defs_TFT_Reset_ILI9481312: ;__Lib_TFT_Defs.mbas,2803 :: TFT_Write_Command_Ptr (0x0A) ORI R25, R0, 10 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2804 :: end if L___Lib_TFT_Defs_TFT_Reset_ILI9481313: J L___Lib_TFT_Defs_TFT_Reset_ILI9481310 NOP ;__Lib_TFT_Defs.mbas,2805 :: else L___Lib_TFT_Defs_TFT_Reset_ILI9481309: ;__Lib_TFT_Defs.mbas,2806 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_ILI9481625 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9481315 NOP L___Lib_TFT_Defs_TFT_Reset_ILI9481625: ;__Lib_TFT_Defs.mbas,2807 :: TFT_Write_Command_Ptr (0x2B) ORI R25, R0, 43 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_ILI9481316 NOP ;__Lib_TFT_Defs.mbas,2808 :: else L___Lib_TFT_Defs_TFT_Reset_ILI9481315: ;__Lib_TFT_Defs.mbas,2809 :: TFT_Write_Command_Ptr (0x28) ORI R25, R0, 40 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2810 :: end if L___Lib_TFT_Defs_TFT_Reset_ILI9481316: ;__Lib_TFT_Defs.mbas,2811 :: end if L___Lib_TFT_Defs_TFT_Reset_ILI9481310: ;__Lib_TFT_Defs.mbas,2813 :: Delay_100ms() Delay_10ms() Delay_10ms() JAL _Delay_100ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,2815 :: TFT_Set_Index_Ptr(0x29) ORI R25, R0, 41 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2818 :: TFT_Set_Index_Ptr(0x2A) ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2819 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2820 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2821 :: TFT_Write_Command_Ptr((TFT_DISP_WIDTH-1) >> 8) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) ADDIU R2, R2, -1 ANDI R2, R2, 65535 SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2822 :: TFT_Write_Command_Ptr(TFT_DISP_WIDTH-1) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) ADDIU R2, R2, -1 ANDI R25, R2, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2824 :: TFT_Set_Index_Ptr(0x2B) ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2825 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2826 :: TFT_Write_Command_Ptr(0) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2827 :: TFT_Write_Command_Ptr((TFT_DISP_HEIGHT-1) >> 8) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) ADDIU R2, R2, -1 ANDI R2, R2, 65535 SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2828 :: TFT_Write_Command_Ptr(TFT_DISP_HEIGHT-1) LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) ADDIU R2, R2, -1 ANDI R25, R2, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2830 :: TFT_Set_Index_Ptr(0x3A) ' pixel format set ORI R25, R0, 58 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2831 :: TFT_Write_Command_Ptr (0x55) ORI R25, R0, 85 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2832 :: TFT_Set_Index_Ptr(0x11) ' Set_address_mode ORI R25, R0, 17 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2833 :: Delay_100ms() Delay_10ms() Delay_10ms() JAL _Delay_100ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,2834 :: Delay_10ms() Delay_10ms() Delay_10ms() JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP JAL _Delay_10ms+0 NOP ;__Lib_TFT_Defs.mbas,2835 :: TFT_Set_Index_Ptr(0x2C) ORI R25, R0, 44 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,2836 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,2837 :: end sub L_end_TFT_Reset_ILI9481: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of __Lib_TFT_Defs_TFT_Reset_ILI9481 _TFT_Init_ILI9481: ;__Lib_TFT_Defs.mbas,2844 :: sub procedure TFT_Init_ILI9481(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2845 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,2846 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9481628 NOP J L__TFT_Init_ILI9481319 NOP L__TFT_Init_ILI9481628: ;__Lib_TFT_Defs.mbas,2847 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2848 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2849 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9481319: ;__Lib_TFT_Defs.mbas,2852 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,2853 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,2854 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9481629 NOP J L__TFT_Init_ILI9481322 NOP L__TFT_Init_ILI9481629: ;__Lib_TFT_Defs.mbas,2855 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9481323 NOP ;__Lib_TFT_Defs.mbas,2856 :: else L__TFT_Init_ILI9481322: ;__Lib_TFT_Defs.mbas,2857 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,2858 :: end if L__TFT_Init_ILI9481323: ;__Lib_TFT_Defs.mbas,2860 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,2861 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,2863 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,2864 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,2865 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,2867 :: TFT_Reset_ILI9481() JAL __Lib_TFT_Defs_TFT_Reset_ILI9481+0 NOP ;__Lib_TFT_Defs.mbas,2868 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9481 LUI R2, hi_addr(_TFT_Set_Address_ILI9481+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9481+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2869 :: end sub L_end_TFT_Init_ILI9481: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9481 _TFT_Init_ILI9481_Custom: ;__Lib_TFT_Defs.mbas,2879 :: sub procedure TFT_Init_ILI9481_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2880 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,2881 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9481_Custom632 NOP J L__TFT_Init_ILI9481_Custom326 NOP L__TFT_Init_ILI9481_Custom632: ;__Lib_TFT_Defs.mbas,2882 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2883 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2884 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9481_Custom326: ;__Lib_TFT_Defs.mbas,2887 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,2888 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,2889 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9481_Custom633 NOP J L__TFT_Init_ILI9481_Custom329 NOP L__TFT_Init_ILI9481_Custom633: ;__Lib_TFT_Defs.mbas,2890 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9481_Custom330 NOP ;__Lib_TFT_Defs.mbas,2891 :: else L__TFT_Init_ILI9481_Custom329: ;__Lib_TFT_Defs.mbas,2892 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,2893 :: end if L__TFT_Init_ILI9481_Custom330: ;__Lib_TFT_Defs.mbas,2895 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,2896 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,2898 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,2899 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,2901 :: TFT_Reset_ILI9481() JAL __Lib_TFT_Defs_TFT_Reset_ILI9481+0 NOP ;__Lib_TFT_Defs.mbas,2902 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9481 LUI R2, hi_addr(_TFT_Set_Address_ILI9481+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9481+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2903 :: end sub L_end_TFT_Init_ILI9481_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9481_Custom _TFT_Init_ILI9481_8bit: ;__Lib_TFT_Defs.mbas,2912 :: sub procedure TFT_Init_ILI9481_8bit(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2913 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,2914 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9481_8bit636 NOP J L__TFT_Init_ILI9481_8bit333 NOP L__TFT_Init_ILI9481_8bit636: ;__Lib_TFT_Defs.mbas,2915 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2916 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2917 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9481_8bit333: ;__Lib_TFT_Defs.mbas,2920 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,2921 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,2922 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9481_8bit637 NOP J L__TFT_Init_ILI9481_8bit336 NOP L__TFT_Init_ILI9481_8bit637: ;__Lib_TFT_Defs.mbas,2923 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9481_8bit337 NOP ;__Lib_TFT_Defs.mbas,2924 :: else L__TFT_Init_ILI9481_8bit336: ;__Lib_TFT_Defs.mbas,2925 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,2926 :: end if L__TFT_Init_ILI9481_8bit337: ;__Lib_TFT_Defs.mbas,2928 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,2929 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,2931 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,2932 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,2933 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,2935 :: TFT_Reset_ILI9481() JAL __Lib_TFT_Defs_TFT_Reset_ILI9481+0 NOP ;__Lib_TFT_Defs.mbas,2936 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9481 LUI R2, hi_addr(_TFT_Set_Address_ILI9481+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9481+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2937 :: end sub L_end_TFT_Init_ILI9481_8bit: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9481_8bit _TFT_Init_ILI9481_8bit_Custom: ;__Lib_TFT_Defs.mbas,2947 :: sub procedure TFT_Init_ILI9481_8bit_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2948 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,2949 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_ILI9481_8bit_Custom640 NOP J L__TFT_Init_ILI9481_8bit_Custom340 NOP L__TFT_Init_ILI9481_8bit_Custom640: ;__Lib_TFT_Defs.mbas,2950 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2951 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2952 :: TFT_Write_Data_Ptr = @TFT_Write_Data LUI R2, hi_addr(_TFT_Write_Data+0) ORI R2, R2, lo_addr(_TFT_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_ILI9481_8bit_Custom340: ;__Lib_TFT_Defs.mbas,2955 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,2956 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,2957 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_ILI9481_8bit_Custom641 NOP J L__TFT_Init_ILI9481_8bit_Custom343 NOP L__TFT_Init_ILI9481_8bit_Custom641: ;__Lib_TFT_Defs.mbas,2958 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_ILI9481_8bit_Custom344 NOP ;__Lib_TFT_Defs.mbas,2959 :: else L__TFT_Init_ILI9481_8bit_Custom343: ;__Lib_TFT_Defs.mbas,2960 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,2961 :: end if L__TFT_Init_ILI9481_8bit_Custom344: ;__Lib_TFT_Defs.mbas,2963 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,2964 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,2966 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,2967 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,2969 :: TFT_Reset_ILI9481() JAL __Lib_TFT_Defs_TFT_Reset_ILI9481+0 NOP ;__Lib_TFT_Defs.mbas,2970 :: TFT_Set_Address_Ptr = @TFT_Set_Address_ILI9481 LUI R2, hi_addr(_TFT_Set_Address_ILI9481+0) ORI R2, R2, lo_addr(_TFT_Set_Address_ILI9481+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,2971 :: end sub L_end_TFT_Init_ILI9481_8bit_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_ILI9481_8bit_Custom _TFT_Set_Address_SSD1963II: ;__Lib_TFT_Defs.mbas,2984 :: dim s_col, e_col, s_page, e_page, _width, _height as word ADDIU SP, SP, -16 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,2988 :: if ((TFT_DISP_WIDTH > 480) or (TFT_DISP_HEIGHT > 480)) then SW R25, 4(SP) LHU R2, Offset(_TFT_DISP_WIDTH+0)(GP) SLTIU R3, R2, 481 XORI R3, R3, 1 BEQ R3, R0, L__TFT_Set_Address_SSD1963II644 NOP ADDIU R3, R0, -1 L__TFT_Set_Address_SSD1963II644: LHU R2, Offset(_TFT_DISP_HEIGHT+0)(GP) SLTIU R2, R2, 481 XORI R2, R2, 1 BEQ R2, R0, L__TFT_Set_Address_SSD1963II646 NOP ADDIU R2, R0, -1 L__TFT_Set_Address_SSD1963II646: OR R2, R3, R2 BNE R2, R0, L__TFT_Set_Address_SSD1963II648 NOP J L__TFT_Set_Address_SSD1963II347 NOP L__TFT_Set_Address_SSD1963II648: ;__Lib_TFT_Defs.mbas,2989 :: _width = 800 ; _width start address is: 20 (R5) ORI R5, R0, 800 ;__Lib_TFT_Defs.mbas,2990 :: _height = 480 ; _height start address is: 16 (R4) ORI R4, R0, 480 ; _height end address is: 16 (R4) ; _width end address is: 20 (R5) J L__TFT_Set_Address_SSD1963II348 NOP ;__Lib_TFT_Defs.mbas,2991 :: else L__TFT_Set_Address_SSD1963II347: ;__Lib_TFT_Defs.mbas,2992 :: _width = 480 ; _width start address is: 20 (R5) ORI R5, R0, 480 ;__Lib_TFT_Defs.mbas,2993 :: _height = 272 ; _height start address is: 16 (R4) ORI R4, R0, 272 ; _height end address is: 16 (R4) ; _width end address is: 20 (R5) ;__Lib_TFT_Defs.mbas,2994 :: end if L__TFT_Set_Address_SSD1963II348: ;__Lib_TFT_Defs.mbas,2995 :: if (TFT_DISP_ROTATION = 90) then ; _height start address is: 16 (R4) ; _width start address is: 20 (R5) LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L__TFT_Set_Address_SSD1963II649 NOP J L__TFT_Set_Address_SSD1963II350 NOP L__TFT_Set_Address_SSD1963II649: ;__Lib_TFT_Defs.mbas,2996 :: if (Is_TFT_Rotated_180()) then JAL _Is_TFT_Rotated_180+0 NOP BNE R2, R0, L__TFT_Set_Address_SSD1963II651 NOP J L__TFT_Set_Address_SSD1963II353 NOP L__TFT_Set_Address_SSD1963II651: ; _height end address is: 16 (R4) ;__Lib_TFT_Defs.mbas,2997 :: s_col = (_width - 1) - y2 ' {TFT_DISP_WIDTH} ADDIU R3, R5, -1 ; _width end address is: 20 (R5) SUBU R2, R3, R28 SH R2, 8(SP) ;__Lib_TFT_Defs.mbas,2998 :: e_col = (_width - 1) - y1 ' {TFT_DISP_WIDTH} SUBU R2, R3, R26 SH R2, 10(SP) ;__Lib_TFT_Defs.mbas,2999 :: s_page = x1 SH R25, 12(SP) ;__Lib_TFT_Defs.mbas,3000 :: e_page = x2 SH R27, 14(SP) J L__TFT_Set_Address_SSD1963II354 NOP ;__Lib_TFT_Defs.mbas,3001 :: else L__TFT_Set_Address_SSD1963II353: ;__Lib_TFT_Defs.mbas,3002 :: s_col = y1 ; _height start address is: 16 (R4) SH R26, 8(SP) ;__Lib_TFT_Defs.mbas,3003 :: e_col = y2 SH R28, 10(SP) ;__Lib_TFT_Defs.mbas,3004 :: s_page = (_height - 1) - x2 ' {TFT_DISP_HEIGHT} ADDIU R3, R4, -1 ; _height end address is: 16 (R4) SUBU R2, R3, R27 SH R2, 12(SP) ;__Lib_TFT_Defs.mbas,3005 :: e_page = (_height - 1) - x1 ' {TFT_DISP_HEIGHT} SUBU R2, R3, R25 SH R2, 14(SP) ;__Lib_TFT_Defs.mbas,3006 :: end if L__TFT_Set_Address_SSD1963II354: J L__TFT_Set_Address_SSD1963II351 NOP ;__Lib_TFT_Defs.mbas,3007 :: else L__TFT_Set_Address_SSD1963II350: ;__Lib_TFT_Defs.mbas,3008 :: if (Is_TFT_Rotated_180()) then ; _width start address is: 20 (R5) ; _height start address is: 16 (R4) JAL _Is_TFT_Rotated_180+0 NOP BNE R2, R0, L__TFT_Set_Address_SSD1963II653 NOP J L__TFT_Set_Address_SSD1963II356 NOP L__TFT_Set_Address_SSD1963II653: ;__Lib_TFT_Defs.mbas,3009 :: s_col = (_width - 1) - x2 ' {TFT_DISP_WIDTH} ADDIU R3, R5, -1 ; _width end address is: 20 (R5) SUBU R2, R3, R27 SH R2, 8(SP) ;__Lib_TFT_Defs.mbas,3010 :: e_col = (_width - 1) - x1 ' {TFT_DISP_WIDTH} SUBU R2, R3, R25 SH R2, 10(SP) ;__Lib_TFT_Defs.mbas,3011 :: s_page = (_height - 1) - y2 ' {TFT_DISP_HEIGHT} ADDIU R3, R4, -1 ; _height end address is: 16 (R4) SUBU R2, R3, R28 SH R2, 12(SP) ;__Lib_TFT_Defs.mbas,3012 :: e_page = (_height - 1) - y1 ' {TFT_DISP_HEIGHT} SUBU R2, R3, R26 SH R2, 14(SP) J L__TFT_Set_Address_SSD1963II357 NOP ;__Lib_TFT_Defs.mbas,3013 :: else L__TFT_Set_Address_SSD1963II356: ;__Lib_TFT_Defs.mbas,3014 :: s_col = x1 SH R25, 8(SP) ;__Lib_TFT_Defs.mbas,3015 :: e_col = x2 SH R27, 10(SP) ;__Lib_TFT_Defs.mbas,3016 :: s_page = y1 SH R26, 12(SP) ;__Lib_TFT_Defs.mbas,3017 :: e_page = y2 SH R28, 14(SP) ;__Lib_TFT_Defs.mbas,3018 :: end if L__TFT_Set_Address_SSD1963II357: ;__Lib_TFT_Defs.mbas,3019 :: end if L__TFT_Set_Address_SSD1963II351: ;__Lib_TFT_Defs.mbas,3020 :: TFT_Set_Index_Ptr(0x2a) ' SET column address ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3021 :: TFT_Write_Command_Ptr(s_col >> 8) LHU R2, 8(SP) SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3022 :: TFT_Write_Command_Ptr(s_col) LHU R25, 8(SP) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3023 :: TFT_Write_Command_Ptr(e_col >> 8) LHU R2, 10(SP) SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3024 :: TFT_Write_Command_Ptr(e_col) LHU R25, 10(SP) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3026 :: TFT_Set_Index_Ptr(0x2b) ' SET page address ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3027 :: TFT_Write_Command_Ptr(s_page >> 8) LHU R2, 12(SP) SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3028 :: TFT_Write_Command_Ptr(s_page) LHU R25, 12(SP) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3029 :: TFT_Write_Command_Ptr(e_page >> 8) LHU R2, 14(SP) SRL R2, R2, 8 ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3030 :: TFT_Write_Command_Ptr(e_page) LHU R25, 14(SP) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3031 :: TFT_Set_Index_Ptr(0x2C) ORI R25, R0, 44 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3032 :: end sub L_end_TFT_Set_Address_SSD1963II: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 16 JR RA NOP ; end of _TFT_Set_Address_SSD1963II _TFT_Set_Address_SSD1963: ;__Lib_TFT_Defs.mbas,3040 :: sub procedure TFT_Set_Address_SSD1963(dim x as word y as word) ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3041 :: TFT_Set_Index_Ptr(0x2a) 'SET column address SW R25, 4(SP) SH R26, 8(SP) SH R25, 10(SP) ORI R25, R0, 42 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,3042 :: TFT_Write_Command_Ptr((x) >> 8) 'SET start column address=0 ANDI R2, R25, 65535 SRL R2, R2, 8 SH R25, 10(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R25, 10(SP) ;__Lib_TFT_Defs.mbas,3043 :: TFT_Write_Command_Ptr(x) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,3044 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L__TFT_Set_Address_SSD1963655 NOP J L__TFT_Set_Address_SSD1963360 NOP L__TFT_Set_Address_SSD1963655: ;__Lib_TFT_Defs.mbas,3045 :: TFT_Write_Command_Ptr(271 >> 8) 'SET end column address=271 SH R26, 8(SP) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3046 :: TFT_Write_Command_Ptr(0x0F) ORI R25, R0, 15 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) J L__TFT_Set_Address_SSD1963361 NOP ;__Lib_TFT_Defs.mbas,3047 :: else L__TFT_Set_Address_SSD1963360: ;__Lib_TFT_Defs.mbas,3048 :: TFT_Write_Command_Ptr(479 >> 8) 'SET end column address=479 SH R26, 8(SP) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3049 :: TFT_Write_Command_Ptr(0xDF) ORI R25, R0, 223 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,3050 :: end if L__TFT_Set_Address_SSD1963361: ;__Lib_TFT_Defs.mbas,3052 :: TFT_Set_Index_Ptr(0x2b) 'SET page address SH R26, 8(SP) ORI R25, R0, 43 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,3053 :: TFT_Write_Command_Ptr((y) >> 8) 'SET start page address=0 ANDI R2, R26, 65535 SRL R2, R2, 8 SH R26, 8(SP) ANDI R25, R2, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LHU R26, 8(SP) ;__Lib_TFT_Defs.mbas,3054 :: TFT_Write_Command_Ptr(y) ANDI R25, R26, 65535 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3055 :: if(TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L__TFT_Set_Address_SSD1963656 NOP J L__TFT_Set_Address_SSD1963363 NOP L__TFT_Set_Address_SSD1963656: ;__Lib_TFT_Defs.mbas,3056 :: TFT_Write_Command_Ptr(479 >> 8) 'SET end page address=479 ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3057 :: TFT_Write_Command_Ptr(0xDF) ORI R25, R0, 223 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L__TFT_Set_Address_SSD1963364 NOP ;__Lib_TFT_Defs.mbas,3058 :: else L__TFT_Set_Address_SSD1963363: ;__Lib_TFT_Defs.mbas,3059 :: TFT_Write_Command_Ptr(271 >> 8) 'SET end page address=271 ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3060 :: TFT_Write_Command_Ptr(0x0F) ORI R25, R0, 15 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3061 :: end if L__TFT_Set_Address_SSD1963364: ;__Lib_TFT_Defs.mbas,3062 :: TFT_Set_Index_Ptr(0x2c) ORI R25, R0, 44 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3063 :: end sub L_end_TFT_Set_Address_SSD1963: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_Set_Address_SSD1963 _TFT_Set_Invert_Mode_SSD1963: ;__Lib_TFT_Defs.mbas,3069 :: sub procedure TFT_Set_Invert_Mode_SSD1963() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3070 :: TFT_CS = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3071 :: TFT_Set_Index_Ptr(0x21) ORI R25, R0, 33 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3072 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3073 :: end sub L_end_TFT_Set_Invert_Mode_SSD1963: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of _TFT_Set_Invert_Mode_SSD1963 _TFT_Exit_Invert_Mode_SSD1963: ;__Lib_TFT_Defs.mbas,3079 :: sub procedure TFT_Exit_Invert_Mode_SSD1963() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3080 :: TFT_CS = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3081 :: TFT_Set_Index_Ptr(0x20) ORI R25, R0, 32 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3082 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3083 :: end sub L_end_TFT_Exit_Invert_Mode_SSD1963: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of _TFT_Exit_Invert_Mode_SSD1963 _TFT_Set_Display_OFF_SSD1963: ;__Lib_TFT_Defs.mbas,3089 :: sub procedure TFT_Set_Display_OFF_SSD1963() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3090 :: TFT_CS = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3091 :: TFT_Set_Index_Ptr(0x28) ORI R25, R0, 40 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3092 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3093 :: end sub L_end_TFT_Set_Display_OFF_SSD1963: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of _TFT_Set_Display_OFF_SSD1963 _TFT_Set_Display_ON_SSD1963: ;__Lib_TFT_Defs.mbas,3099 :: sub procedure TFT_Set_Display_ON_SSD1963() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3100 :: TFT_CS = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3101 :: TFT_Set_Index_Ptr(0x29) ORI R25, R0, 41 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3102 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3103 :: end sub L_end_TFT_Set_Display_ON_SSD1963: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of _TFT_Set_Display_ON_SSD1963 _TFT_Enter_Sleep_Mode_SSD1963: ;__Lib_TFT_Defs.mbas,3109 :: sub procedure TFT_Enter_Sleep_Mode_SSD1963() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3110 :: TFT_CS = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3111 :: TFT_Set_Index_Ptr(0x10) ORI R25, R0, 16 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3112 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3115 :: Delay_5ms() JAL _Delay_5ms+0 NOP ;__Lib_TFT_Defs.mbas,3116 :: end sub L_end_TFT_Enter_Sleep_Mode_SSD1963: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of _TFT_Enter_Sleep_Mode_SSD1963 _TFT_Exit_Sleep_Mode_SSD1963: ;__Lib_TFT_Defs.mbas,3122 :: sub procedure TFT_Exit_Sleep_Mode_SSD1963() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3123 :: TFT_CS = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3124 :: TFT_Set_Index_Ptr(0x11) ORI R25, R0, 17 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3125 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3126 :: end sub L_end_TFT_Exit_Sleep_Mode_SSD1963: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of _TFT_Exit_Sleep_Mode_SSD1963 _TFT_Enter_Normal_Mode_SSD1963: ;__Lib_TFT_Defs.mbas,3132 :: sub procedure TFT_Enter_Normal_Mode_SSD1963() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3133 :: TFT_CS = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3134 :: TFT_Set_Index_Ptr(0x13) ORI R25, R0, 19 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3135 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3136 :: end sub L_end_TFT_Enter_Normal_Mode_SSD1963: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of _TFT_Enter_Normal_Mode_SSD1963 _TFT_Enter_Idle_Mode_SSD1963: ;__Lib_TFT_Defs.mbas,3142 :: sub procedure TFT_Enter_Idle_Mode_SSD1963() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3143 :: TFT_CS = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3144 :: TFT_Set_Index_Ptr(0x39) ORI R25, R0, 57 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3145 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3146 :: end sub L_end_TFT_Enter_Idle_Mode_SSD1963: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of _TFT_Enter_Idle_Mode_SSD1963 _TFT_Exit_Idle_Mode_SSD1963: ;__Lib_TFT_Defs.mbas,3149 :: sub procedure TFT_Exit_Idle_Mode_SSD1963() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3150 :: TFT_CS = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3151 :: TFT_Set_Index_Ptr(0x38) ORI R25, R0, 56 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3152 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3153 :: end sub L_end_TFT_Exit_Idle_Mode_SSD1963: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of _TFT_Exit_Idle_Mode_SSD1963 _TFT_Set_DBC_SSD1963: ;__Lib_TFT_Defs.mbas,3161 :: sub procedure TFT_Set_DBC_SSD1963(dim value as byte) ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3162 :: TFT_CS = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3163 :: TFT_Set_Index_Ptr(0xBE) SB R25, 8(SP) ORI R25, R0, 190 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3164 :: TFT_Write_Command_Ptr(0x06) ORI R25, R0, 6 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP LBU R25, 8(SP) ;__Lib_TFT_Defs.mbas,3165 :: TFT_Write_Command_Ptr(value) LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3166 :: TFT_Write_Command_Ptr(0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3167 :: TFT_Write_Command_Ptr(0xFF) ORI R25, R0, 255 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3168 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3169 :: TFT_Write_Command_Ptr(0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3170 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3171 :: end sub L_end_TFT_Set_DBC_SSD1963: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_Set_DBC_SSD1963 __Lib_TFT_Defs_TFT_Reset_SSD1963: ;__Lib_TFT_Defs.mbas,3177 :: sub procedure TFT_Reset_SSD1963() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3179 :: TFT_RST = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,3181 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,3184 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,3186 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,3189 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3191 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,3193 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,3194 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,3195 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,3196 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,3198 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,3199 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,3200 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,3201 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,3203 :: TFT_CS = 0 _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3204 :: TFT_Set_Index_Ptr(0x01) 'Software Reset ORI R25, R0, 1 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3205 :: TFT_Set_Index_Ptr(0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3206 :: TFT_Set_Index_Ptr(0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3208 :: TFT_Set_Index_Ptr(0xE2) ORI R25, R0, 226 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3209 :: TFT_Write_Command_Ptr(35) ' PLLclk = REFclk * 36 (360MHz) ORI R25, R0, 35 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3210 :: TFT_Write_Command_Ptr(2) ' SYSclk = PLLclk / 3 (120MHz) ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3211 :: TFT_Write_Command_Ptr(0x54) ' validate M and N ORI R25, R0, 84 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3216 :: TFT_Set_Index_Ptr(0xe0) ORI R25, R0, 224 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3217 :: TFT_Write_Command_Ptr(0x01) ' START PLL ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3219 :: Delay_50us() Delay_50us() JAL _Delay_50uS+0 NOP JAL _Delay_50uS+0 NOP ;__Lib_TFT_Defs.mbas,3221 :: TFT_Set_Index_Ptr(0xe0) ORI R25, R0, 224 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3222 :: TFT_Write_Command_Ptr(0x03) ' LOCK PLL ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3224 :: TFT_Set_Index_Ptr(0xb0) 'SET LCD MODE SET TFT 18Bits MODE ORI R25, R0, 176 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3225 :: if (Is_TFT_MM_Plus = 0) then JAL _Is_TFT_MM_Plus+0 NOP ANDI R2, R2, 255 BEQ R2, R0, L___Lib_TFT_Defs_TFT_Reset_SSD1963668 NOP J L___Lib_TFT_Defs_TFT_Reset_SSD1963377 NOP L___Lib_TFT_Defs_TFT_Reset_SSD1963668: ;__Lib_TFT_Defs.mbas,3226 :: TFT_Write_Command_Ptr(0x08) 'SET TFT MODE & hsync+Vsync+DEN MODE ORI R25, R0, 8 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3227 :: TFT_Write_Command_Ptr(0x80) 'SET TFT MODE & hsync+Vsync+DEN MODE ORI R25, R0, 128 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_SSD1963378 NOP ;__Lib_TFT_Defs.mbas,3228 :: else L___Lib_TFT_Defs_TFT_Reset_SSD1963377: ;__Lib_TFT_Defs.mbas,3229 :: TFT_Write_Command_Ptr(0x28) 'SET TFT MODE & hsync+Vsync+DEN MODE ORI R25, R0, 40 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3230 :: TFT_Write_Command_Ptr(0x20) 'SET TFT MODE & hsync+Vsync+DEN MODE ORI R25, R0, 32 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3231 :: end if L___Lib_TFT_Defs_TFT_Reset_SSD1963378: ;__Lib_TFT_Defs.mbas,3232 :: TFT_Write_Command_Ptr(0x01) 'SET horizontal size=480-1 HightByte ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3233 :: TFT_Write_Command_Ptr(0xdf) 'SET horizontal size=480-1 LowByte ORI R25, R0, 223 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3234 :: TFT_Write_Command_Ptr(0x01) 'SET vertical size=272-1 HightByte ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3235 :: TFT_Write_Command_Ptr(0x0f) 'SET vertical size=272-1 LowByte ORI R25, R0, 15 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3236 :: TFT_Write_Command_Ptr(0x00) 'SET even/odd line RGB seq.=RGB MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3238 :: TFT_Set_Index_Ptr(0xf0) ORI R25, R0, 240 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3239 :: TFT_Write_Command_Ptr(0x03) '3 -16bit,0 -8bit 'SET pixel data I/F format=8bit ORI R25, R0, 3 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3240 :: TFT_Set_Index_Ptr(0x3A) ORI R25, R0, 58 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3241 :: TFT_Write_Command_Ptr(0x60) ' SET R G B format = 6 6 6 ORI R25, R0, 96 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3246 :: TFT_Set_Index_Ptr(0xe6) 'SET PCLK freq=10MHz pixel clock frequency ORI R25, R0, 230 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3247 :: TFT_Write_Command_Ptr(0x01) ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3248 :: TFT_Write_Command_Ptr(0x45) ORI R25, R0, 69 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3249 :: TFT_Write_Command_Ptr(0x47) ORI R25, R0, 71 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3251 :: TFT_Set_Index_Ptr(0xb4) 'SET HBP, ORI R25, R0, 180 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3252 :: TFT_Write_Command_Ptr(0x02) 'SET HSYNC Tatol 525 ORI R25, R0, 2 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3253 :: TFT_Write_Command_Ptr(0x0d) ORI R25, R0, 13 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3254 :: TFT_Write_Command_Ptr(0x00) 'SET HBP 43 MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3255 :: TFT_Write_Command_Ptr(0x2b) ORI R25, R0, 43 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3256 :: TFT_Write_Command_Ptr(0x28) 'SET VBP 41=40+1 ORI R25, R0, 40 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3257 :: TFT_Write_Command_Ptr(0x00) 'SET Hsync pulse start position MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3258 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3259 :: TFT_Write_Command_Ptr(0x00) 'SET Hsync pulse subpixel start position MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3261 :: TFT_Set_Index_Ptr(0xb6) 'SET VBP, ORI R25, R0, 182 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3262 :: TFT_Write_Command_Ptr(0x01) 'SET Vsync total 286=285+1 ORI R25, R0, 1 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3263 :: TFT_Write_Command_Ptr(0x1d) ORI R25, R0, 29 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3264 :: TFT_Write_Command_Ptr(0x00) 'SET VBP=12 MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3265 :: TFT_Write_Command_Ptr(0x0c) ORI R25, R0, 12 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3266 :: TFT_Write_Command_Ptr(0x09) 'SET Vsync pulse 10=9+1 ORI R25, R0, 9 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3267 :: TFT_Write_Command_Ptr(0x00) 'SET Vsync pulse start position MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3268 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3270 :: TFT_Set_Index_Ptr(0x36) ' memory access control ORI R25, R0, 54 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3271 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_SSD1963669 NOP J L___Lib_TFT_Defs_TFT_Reset_SSD1963380 NOP L___Lib_TFT_Defs_TFT_Reset_SSD1963669: ;__Lib_TFT_Defs.mbas,3272 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_SSD1963670 NOP J L___Lib_TFT_Defs_TFT_Reset_SSD1963383 NOP L___Lib_TFT_Defs_TFT_Reset_SSD1963670: ;__Lib_TFT_Defs.mbas,3273 :: TFT_Write_Command_Ptr(0x60) ORI R25, R0, 96 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_SSD1963384 NOP ;__Lib_TFT_Defs.mbas,3274 :: else L___Lib_TFT_Defs_TFT_Reset_SSD1963383: ;__Lib_TFT_Defs.mbas,3275 :: TFT_Write_Command_Ptr(0xA0) ORI R25, R0, 160 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3276 :: end if L___Lib_TFT_Defs_TFT_Reset_SSD1963384: J L___Lib_TFT_Defs_TFT_Reset_SSD1963381 NOP ;__Lib_TFT_Defs.mbas,3277 :: else L___Lib_TFT_Defs_TFT_Reset_SSD1963380: ;__Lib_TFT_Defs.mbas,3278 :: if (Is_TFT_Rotated_180() = 1) then JAL _Is_TFT_Rotated_180+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_SSD1963671 NOP J L___Lib_TFT_Defs_TFT_Reset_SSD1963386 NOP L___Lib_TFT_Defs_TFT_Reset_SSD1963671: ;__Lib_TFT_Defs.mbas,3279 :: TFT_Write_Command_Ptr(0xC0) ORI R25, R0, 192 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP J L___Lib_TFT_Defs_TFT_Reset_SSD1963387 NOP ;__Lib_TFT_Defs.mbas,3280 :: else L___Lib_TFT_Defs_TFT_Reset_SSD1963386: ;__Lib_TFT_Defs.mbas,3281 :: TFT_Write_Command_Ptr(0x00) MOVZ R25, R0, R0 LW R30, Offset(_TFT_Write_Command_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3282 :: end if L___Lib_TFT_Defs_TFT_Reset_SSD1963387: ;__Lib_TFT_Defs.mbas,3283 :: end if L___Lib_TFT_Defs_TFT_Reset_SSD1963381: ;__Lib_TFT_Defs.mbas,3285 :: TFT_Set_Index_Ptr(0x29) 'SET display on ORI R25, R0, 41 LW R30, Offset(_TFT_Set_Index_Ptr+0)(GP) JALR RA, R30 NOP ;__Lib_TFT_Defs.mbas,3286 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3287 :: end sub L_end_TFT_Reset_SSD1963: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of __Lib_TFT_Defs_TFT_Reset_SSD1963 _TFT_Init_SSD1963: ;__Lib_TFT_Defs.mbas,3294 :: sub procedure TFT_Init_SSD1963(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3295 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,3296 :: TFT_Set_SSD1963() JAL _TFT_Set_SSD1963+0 NOP ;__Lib_TFT_Defs.mbas,3297 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_SSD1963674 NOP J L__TFT_Init_SSD1963390 NOP L__TFT_Init_SSD1963674: ;__Lib_TFT_Defs.mbas,3298 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3299 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3300 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_SSD1963390: ;__Lib_TFT_Defs.mbas,3303 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,3304 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,3305 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_SSD1963675 NOP J L__TFT_Init_SSD1963393 NOP L__TFT_Init_SSD1963675: ;__Lib_TFT_Defs.mbas,3306 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_SSD1963394 NOP ;__Lib_TFT_Defs.mbas,3307 :: else L__TFT_Init_SSD1963393: ;__Lib_TFT_Defs.mbas,3308 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,3309 :: end if L__TFT_Init_SSD1963394: ;__Lib_TFT_Defs.mbas,3311 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,3312 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,3314 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,3315 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,3316 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,3318 :: TFT_Reset_SSD1963() JAL __Lib_TFT_Defs_TFT_Reset_SSD1963+0 NOP ;__Lib_TFT_Defs.mbas,3319 :: TFT_SSD1963_Set_Address_Ptr = @TFT_Set_Address_SSD1963II LUI R2, hi_addr(_TFT_Set_Address_SSD1963II+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SSD1963II+0) SW R2, Offset(_TFT_SSD1963_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3320 :: end sub L_end_TFT_Init_SSD1963: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_SSD1963 _TFT_Init_SSD1963_Custom: ;__Lib_TFT_Defs.mbas,3330 :: sub procedure TFT_Init_SSD1963_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3331 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,3332 :: TFT_Set_SSD1963() JAL _TFT_Set_SSD1963+0 NOP ;__Lib_TFT_Defs.mbas,3333 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_SSD1963_Custom678 NOP J L__TFT_Init_SSD1963_Custom397 NOP L__TFT_Init_SSD1963_Custom678: ;__Lib_TFT_Defs.mbas,3334 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3335 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3336 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_SSD1963_Custom397: ;__Lib_TFT_Defs.mbas,3339 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,3340 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,3341 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_SSD1963_Custom679 NOP J L__TFT_Init_SSD1963_Custom400 NOP L__TFT_Init_SSD1963_Custom679: ;__Lib_TFT_Defs.mbas,3342 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_SSD1963_Custom401 NOP ;__Lib_TFT_Defs.mbas,3343 :: else L__TFT_Init_SSD1963_Custom400: ;__Lib_TFT_Defs.mbas,3344 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,3345 :: end if L__TFT_Init_SSD1963_Custom401: ;__Lib_TFT_Defs.mbas,3347 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,3348 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,3350 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,3351 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,3353 :: TFT_Reset_SSD1963() JAL __Lib_TFT_Defs_TFT_Reset_SSD1963+0 NOP ;__Lib_TFT_Defs.mbas,3354 :: TFT_SSD1963_Set_Address_Ptr = @TFT_Set_Address_SSD1963II LUI R2, hi_addr(_TFT_Set_Address_SSD1963II+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SSD1963II+0) SW R2, Offset(_TFT_SSD1963_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3355 :: end sub L_end_TFT_Init_SSD1963_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_SSD1963_Custom _TFT_SSD1963_8bit_Set_Index: ;__Lib_TFT_Defs.mbas,3363 :: sub procedure TFT_SSD1963_8bit_Set_Index(dim index as byte) ADDIU SP, SP, -4 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3364 :: Delay_1us() JAL _Delay_1uS+0 NOP ;__Lib_TFT_Defs.mbas,3365 :: Delay_1us() JAL _Delay_1uS+0 NOP ;__Lib_TFT_Defs.mbas,3366 :: TFT_CS = 0 _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3367 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,3368 :: TFT_RS = 0 _LX INS R2, R0, BitPos(TFT_RS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3369 :: TFT_DataPort = index SB R25, Offset(TFT_DataPort+0)(GP) ;__Lib_TFT_Defs.mbas,3370 :: TFT_WR = 0 _LX INS R2, R0, BitPos(TFT_WR+0), 1 _SX ;__Lib_TFT_Defs.mbas,3371 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,3372 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3373 :: end sub L_end_TFT_SSD1963_8bit_Set_Index: LW RA, 0(SP) ADDIU SP, SP, 4 JR RA NOP ; end of _TFT_SSD1963_8bit_Set_Index _TFT_SSD1963YT_8bit_Write_Command: ;__Lib_TFT_Defs.mbas,3379 :: sub procedure TFT_SSD1963YT_8bit_Write_Command(dim command_ as byte) ADDIU SP, SP, -4 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3380 :: TFT_CS = 0 _LX INS R2, R0, BitPos(TFT_CS+0), 1 _SX ;__Lib_TFT_Defs.mbas,3381 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,3382 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,3383 :: TFT_DataPort = command_ SB R25, Offset(TFT_DataPort+0)(GP) ;__Lib_TFT_Defs.mbas,3384 :: TFT_WR = 0 _LX INS R2, R0, BitPos(TFT_WR+0), 1 _SX ;__Lib_TFT_Defs.mbas,3385 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,3386 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3387 :: Delay_1us() JAL _Delay_1uS+0 NOP ;__Lib_TFT_Defs.mbas,3388 :: Delay_1us() JAL _Delay_1uS+0 NOP ;__Lib_TFT_Defs.mbas,3389 :: end sub L_end_TFT_SSD1963YT_8bit_Write_Command: LW RA, 0(SP) ADDIU SP, SP, 4 JR RA NOP ; end of _TFT_SSD1963YT_8bit_Write_Command _TFT_SSD1963_8bit_Write_Data: ;__Lib_TFT_Defs.mbas,3392 :: dim temp as byte volatile ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3393 :: temp = (color >> 11) SW R25, 4(SP) ANDI R2, R25, 65535 SRL R2, R2, 11 ; temp start address is: 12 (R3) ANDI R3, R2, 65535 ;__Lib_TFT_Defs.mbas,3394 :: temp = (temp << 3) ANDI R2, R3, 255 ; temp end address is: 12 (R3) SLL R2, R2, 3 ; temp start address is: 16 (R4) ANDI R4, R2, 255 ;__Lib_TFT_Defs.mbas,3395 :: if ((temp >> 7) = 1) then ANDI R2, R4, 255 SRL R2, R2, 7 ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L__TFT_SSD1963_8bit_Write_Data683 NOP J L__TFT_SSD1963_8bit_Write_Data455 NOP L__TFT_SSD1963_8bit_Write_Data683: ;__Lib_TFT_Defs.mbas,3396 :: temp = temp + 7 ADDIU R2, R4, 7 ; temp end address is: 16 (R4) ; temp start address is: 12 (R3) ANDI R3, R2, 255 ; temp end address is: 12 (R3) ANDI R2, R3, 255 J L__TFT_SSD1963_8bit_Write_Data406 NOP L__TFT_SSD1963_8bit_Write_Data455: ;__Lib_TFT_Defs.mbas,3395 :: if ((temp >> 7) = 1) then ANDI R2, R4, 255 ;__Lib_TFT_Defs.mbas,3396 :: temp = temp + 7 L__TFT_SSD1963_8bit_Write_Data406: ;__Lib_TFT_Defs.mbas,3398 :: TFT_SSD1963YT_8bit_Write_Command(temp) ; temp start address is: 8 (R2) SH R25, 8(SP) ; temp end address is: 8 (R2) ANDI R25, R2, 255 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP LHU R25, 8(SP) ;__Lib_TFT_Defs.mbas,3399 :: temp = (color >> 5) ANDI R2, R25, 65535 SRL R2, R2, 5 ; temp start address is: 12 (R3) ANDI R3, R2, 65535 ;__Lib_TFT_Defs.mbas,3400 :: temp = (temp << 2) ANDI R2, R3, 255 ; temp end address is: 12 (R3) SLL R2, R2, 2 ; temp start address is: 16 (R4) ANDI R4, R2, 255 ;__Lib_TFT_Defs.mbas,3401 :: if ((temp >> 7) = 1) then ANDI R2, R4, 255 SRL R2, R2, 7 ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L__TFT_SSD1963_8bit_Write_Data684 NOP J L__TFT_SSD1963_8bit_Write_Data456 NOP L__TFT_SSD1963_8bit_Write_Data684: ;__Lib_TFT_Defs.mbas,3402 :: temp = temp + 3 ADDIU R2, R4, 3 ; temp end address is: 16 (R4) ; temp start address is: 12 (R3) ANDI R3, R2, 255 ; temp end address is: 12 (R3) ANDI R2, R3, 255 J L__TFT_SSD1963_8bit_Write_Data409 NOP L__TFT_SSD1963_8bit_Write_Data456: ;__Lib_TFT_Defs.mbas,3401 :: if ((temp >> 7) = 1) then ANDI R2, R4, 255 ;__Lib_TFT_Defs.mbas,3402 :: temp = temp + 3 L__TFT_SSD1963_8bit_Write_Data409: ;__Lib_TFT_Defs.mbas,3405 :: TFT_SSD1963YT_8bit_Write_Command(temp) ; temp start address is: 8 (R2) SH R25, 8(SP) ; temp end address is: 8 (R2) ANDI R25, R2, 255 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP LHU R25, 8(SP) ;__Lib_TFT_Defs.mbas,3406 :: temp = (color << 3) ANDI R2, R25, 65535 SLL R2, R2, 3 ; temp start address is: 16 (R4) ANDI R4, R2, 255 ;__Lib_TFT_Defs.mbas,3407 :: if ((temp >> 7) = 1) then ANDI R2, R4, 255 SRL R2, R2, 7 ANDI R3, R2, 255 ORI R2, R0, 1 BEQ R3, R2, L__TFT_SSD1963_8bit_Write_Data685 NOP J L__TFT_SSD1963_8bit_Write_Data457 NOP L__TFT_SSD1963_8bit_Write_Data685: ;__Lib_TFT_Defs.mbas,3408 :: temp = temp + 7 ADDIU R2, R4, 7 ; temp end address is: 16 (R4) ; temp start address is: 12 (R3) ANDI R3, R2, 255 ; temp end address is: 12 (R3) ANDI R2, R3, 255 J L__TFT_SSD1963_8bit_Write_Data412 NOP L__TFT_SSD1963_8bit_Write_Data457: ;__Lib_TFT_Defs.mbas,3407 :: if ((temp >> 7) = 1) then ANDI R2, R4, 255 ;__Lib_TFT_Defs.mbas,3408 :: temp = temp + 7 L__TFT_SSD1963_8bit_Write_Data412: ;__Lib_TFT_Defs.mbas,3411 :: TFT_SSD1963YT_8bit_Write_Command(temp) ; temp start address is: 8 (R2) ANDI R25, R2, 255 ; temp end address is: 8 (R2) JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3412 :: end sub L_end_TFT_SSD1963_8bit_Write_Data: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_SSD1963_8bit_Write_Data _TFT_SSD1963_8bit_Set_Reg: ;__Lib_TFT_Defs.mbas,3419 :: sub procedure TFT_SSD1963_8bit_Set_Reg(dim command_ as byte data1 as byte) ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3420 :: TFT_SSD1963_8bit_Set_Index(command_) SW R25, 4(SP) JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3421 :: TFT_SSD1963YT_8bit_Write_Command(data1) ANDI R25, R26, 255 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3422 :: end sub L_end_TFT_SSD1963_8bit_Set_Reg: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of _TFT_SSD1963_8bit_Set_Reg _TFT_Set_Address_SSD1963_8bit: ;__Lib_TFT_Defs.mbas,3429 :: sub procedure TFT_Set_Address_SSD1963_8bit(dim x as word y as word) ADDIU SP, SP, -12 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3430 :: TFT_SSD1963_8bit_Set_Index(0x2A) ' SET column address SW R25, 4(SP) SH R25, 8(SP) ORI R25, R0, 42 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP LHU R25, 8(SP) ;__Lib_TFT_Defs.mbas,3431 :: TFT_SSD1963YT_8bit_Write_Command((x) >> 8) ' SET start page address=0 ANDI R2, R25, 65535 SRL R2, R2, 8 SH R25, 8(SP) ANDI R25, R2, 65535 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP LHU R25, 8(SP) ;__Lib_TFT_Defs.mbas,3432 :: TFT_SSD1963YT_8bit_Write_Command(x) JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3433 :: TFT_SSD1963YT_8bit_Write_Command(0x03) ' SET start column address=0 ORI R25, R0, 3 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3434 :: TFT_SSD1963YT_8bit_Write_Command(0x1F) ORI R25, R0, 31 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3435 :: TFT_SSD1963_8bit_Set_Index(0x2B) ' SET page address ORI R25, R0, 43 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3436 :: TFT_SSD1963YT_8bit_Write_Command((y) >> 8) ' SET start column address=0 ANDI R2, R26, 65535 SRL R2, R2, 8 ANDI R25, R2, 65535 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3437 :: TFT_SSD1963YT_8bit_Write_Command(y) ANDI R25, R26, 65535 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3438 :: TFT_SSD1963YT_8bit_Write_Command(0x01) ' SET start page address=0 ORI R25, R0, 1 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3439 :: TFT_SSD1963YT_8bit_Write_Command(0xDF) ORI R25, R0, 223 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3440 :: TFT_SSD1963_8bit_Set_Index(0x2C) ORI R25, R0, 44 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3441 :: end sub L_end_TFT_Set_Address_SSD1963_8bit: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 12 JR RA NOP ; end of _TFT_Set_Address_SSD1963_8bit __Lib_TFT_Defs_TFT_Reset_SSD1963_8bit: ;__Lib_TFT_Defs.mbas,3447 :: sub procedure TFT_Reset_SSD1963_8bit() ADDIU SP, SP, -8 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3449 :: TFT_RST = 0 SW R25, 4(SP) _LX INS R2, R0, BitPos(TFT_RST+0), 1 _SX ;__Lib_TFT_Defs.mbas,3451 :: TFT_RST_Direction = 0 _LX INS R2, R0, BitPos(TFT_RST_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,3454 :: TFT_RS = 1 _LX ORI R2, R2, BitMask(TFT_RS+0) _SX ;__Lib_TFT_Defs.mbas,3456 :: TFT_RS_Direction = 0 _LX INS R2, R0, BitPos(TFT_RS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,3459 :: TFT_CS = 1 _LX ORI R2, R2, BitMask(TFT_CS+0) _SX ;__Lib_TFT_Defs.mbas,3461 :: TFT_CS_Direction = 0 _LX INS R2, R0, BitPos(TFT_CS_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,3463 :: TFT_RD_Direction = 0 _LX INS R2, R0, BitPos(TFT_RD_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,3464 :: TFT_WR_Direction = 0 _LX INS R2, R0, BitPos(TFT_WR_Direction+0), 1 _SX ;__Lib_TFT_Defs.mbas,3465 :: TFT_RD = 1 _LX ORI R2, R2, BitMask(TFT_RD+0) _SX ;__Lib_TFT_Defs.mbas,3466 :: TFT_WR = 1 _LX ORI R2, R2, BitMask(TFT_WR+0) _SX ;__Lib_TFT_Defs.mbas,3469 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,3470 :: TFT_RST = 1 _LX ORI R2, R2, BitMask(TFT_RST+0) _SX ;__Lib_TFT_Defs.mbas,3471 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,3472 :: Delay_100ms() JAL _Delay_100ms+0 NOP ;__Lib_TFT_Defs.mbas,3474 :: TFT_SSD1963_8bit_Set_Index(0x01) 'Software Reset ORI R25, R0, 1 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3475 :: TFT_SSD1963_8bit_Set_Index(0x01) ORI R25, R0, 1 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3476 :: TFT_SSD1963_8bit_Set_Index(0x01) ORI R25, R0, 1 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3478 :: TFT_SSD1963_8bit_Set_Index(0xe0) 'START PLL ORI R25, R0, 224 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3479 :: TFT_SSD1963YT_8bit_Write_Command(0x01) ORI R25, R0, 1 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3481 :: Delay_50us() Delay_50us() JAL _Delay_50uS+0 NOP JAL _Delay_50uS+0 NOP ;__Lib_TFT_Defs.mbas,3482 :: TFT_SSD1963_8bit_Set_Index(0xe0)'LOCK PLL ORI R25, R0, 224 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3483 :: TFT_SSD1963YT_8bit_Write_Command(0x03) ORI R25, R0, 3 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3484 :: TFT_SSD1963_8bit_Set_Index(0xb0) 'SET LCD MODE SET TFT 18Bits MODE ORI R25, R0, 176 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3485 :: TFT_SSD1963YT_8bit_Write_Command(0x08) 'SET TFT MODE & hsync+Vsync+DEN ORI R25, R0, 8 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3487 :: TFT_SSD1963YT_8bit_Write_Command(0x80) 'SET TFT MODE & hsync+Vsync+DEN ORI R25, R0, 128 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3489 :: TFT_SSD1963YT_8bit_Write_Command(0x03) 'SET horizontal size ORI R25, R0, 3 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3491 :: TFT_SSD1963YT_8bit_Write_Command(0x1f) 'SET horizontal size ORI R25, R0, 31 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3493 :: TFT_SSD1963YT_8bit_Write_Command(0x01) 'SET vertical size ORI R25, R0, 1 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3495 :: TFT_SSD1963YT_8bit_Write_Command(0xdf) 'SET vertical size LowByte ORI R25, R0, 223 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3496 :: TFT_SSD1963YT_8bit_Write_Command(0x2d) 'SET even/odd line RGB seq.=RGB ORI R25, R0, 45 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3497 :: TFT_SSD1963_8bit_Set_Index(0xF0) ORI R25, R0, 240 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3498 :: TFT_SSD1963YT_8bit_Write_Command(0x00) MOVZ R25, R0, R0 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3500 :: TFT_SSD1963_8bit_Set_Index(0x3A) ORI R25, R0, 58 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3501 :: TFT_SSD1963YT_8bit_Write_Command(0x60) ORI R25, R0, 96 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3503 :: TFT_SSD1963_8bit_Set_Index(0xe6) 'SET PCLK freq=33.26MHz ORI R25, R0, 230 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3504 :: TFT_SSD1963YT_8bit_Write_Command(0x02) ORI R25, R0, 2 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3505 :: TFT_SSD1963YT_8bit_Write_Command(0xef) ORI R25, R0, 239 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3506 :: TFT_SSD1963YT_8bit_Write_Command(0xff) ORI R25, R0, 255 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3508 :: TFT_SSD1963_8bit_Set_Index(0xb4) 'SET HBP, HFP ORI R25, R0, 180 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3509 :: TFT_SSD1963YT_8bit_Write_Command(0x20) 'SET HSYNC ORI R25, R0, 32 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3510 :: TFT_SSD1963YT_8bit_Write_Command(0xaf) ORI R25, R0, 175 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3511 :: TFT_SSD1963YT_8bit_Write_Command(0x00) 'SET HBP MOVZ R25, R0, R0 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3512 :: TFT_SSD1963YT_8bit_Write_Command(0xa3) ORI R25, R0, 163 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3513 :: TFT_SSD1963YT_8bit_Write_Command(0x07) 'SET VBP ORI R25, R0, 7 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3514 :: TFT_SSD1963YT_8bit_Write_Command(0x00) 'SET Hsync pulse start position MOVZ R25, R0, R0 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3515 :: TFT_SSD1963YT_8bit_Write_Command(0x00) MOVZ R25, R0, R0 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3516 :: TFT_SSD1963YT_8bit_Write_Command(0x00) 'SET Hsync pulse subpixel start MOVZ R25, R0, R0 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3518 :: TFT_SSD1963_8bit_Set_Index(0xb6) 'SET VBP, VFP ORI R25, R0, 182 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3519 :: TFT_SSD1963YT_8bit_Write_Command(0x01) 'SET Vsync ORI R25, R0, 1 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3520 :: TFT_SSD1963YT_8bit_Write_Command(0xef) ORI R25, R0, 239 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3521 :: TFT_SSD1963YT_8bit_Write_Command(0x00) 'SET VBP MOVZ R25, R0, R0 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3522 :: TFT_SSD1963YT_8bit_Write_Command(0x04) ORI R25, R0, 4 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3523 :: TFT_SSD1963YT_8bit_Write_Command(0x01) 'SET Vsync pulse ORI R25, R0, 1 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3524 :: TFT_SSD1963YT_8bit_Write_Command(0x00) 'SET Vsync pulse start position MOVZ R25, R0, R0 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3525 :: TFT_SSD1963YT_8bit_Write_Command(0x00) MOVZ R25, R0, R0 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3527 :: TFT_SSD1963_8bit_Set_Index(0x36) ' memory access control ORI R25, R0, 54 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3528 :: if (TFT_Disp_Rotation = 90) then LBU R3, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ORI R2, R0, 90 BEQ R3, R2, L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit689 NOP J L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit418 NOP L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit689: ;__Lib_TFT_Defs.mbas,3529 :: if (Is_TFT_Rotated_180()) then JAL _Is_TFT_Rotated_180+0 NOP BNE R2, R0, L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit691 NOP J L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit421 NOP L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit691: ;__Lib_TFT_Defs.mbas,3530 :: TFT_SSD1963YT_8bit_Write_Command(0x60) ORI R25, R0, 96 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP J L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit422 NOP ;__Lib_TFT_Defs.mbas,3531 :: else L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit421: ;__Lib_TFT_Defs.mbas,3532 :: TFT_SSD1963YT_8bit_Write_Command(0xA0) ORI R25, R0, 160 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3533 :: end if L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit422: J L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit419 NOP ;__Lib_TFT_Defs.mbas,3534 :: else L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit418: ;__Lib_TFT_Defs.mbas,3535 :: if (Is_TFT_Rotated_180()) then JAL _Is_TFT_Rotated_180+0 NOP BNE R2, R0, L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit693 NOP J L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit424 NOP L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit693: ;__Lib_TFT_Defs.mbas,3536 :: TFT_SSD1963YT_8bit_Write_Command(0xC0) ORI R25, R0, 192 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP J L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit425 NOP ;__Lib_TFT_Defs.mbas,3537 :: else L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit424: ;__Lib_TFT_Defs.mbas,3538 :: TFT_SSD1963YT_8bit_Write_Command(0x00) MOVZ R25, R0, R0 JAL _TFT_SSD1963YT_8bit_Write_Command+0 NOP ;__Lib_TFT_Defs.mbas,3539 :: end if L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit425: ;__Lib_TFT_Defs.mbas,3540 :: end if L___Lib_TFT_Defs_TFT_Reset_SSD1963_8bit419: ;__Lib_TFT_Defs.mbas,3542 :: TFT_SSD1963_8bit_Set_Index(0x29) 'SET display on ORI R25, R0, 41 JAL _TFT_SSD1963_8bit_Set_Index+0 NOP ;__Lib_TFT_Defs.mbas,3543 :: end sub L_end_TFT_Reset_SSD1963_8bit: LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 8 JR RA NOP ; end of __Lib_TFT_Defs_TFT_Reset_SSD1963_8bit _TFT_Init_SSD1963_8bit: ;__Lib_TFT_Defs.mbas,3550 :: sub procedure TFT_Init_SSD1963_8bit(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3551 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,3552 :: TFT_Set_SSD1963() JAL _TFT_Set_SSD1963+0 NOP ;__Lib_TFT_Defs.mbas,3553 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_SSD1963_8bit696 NOP J L__TFT_Init_SSD1963_8bit428 NOP L__TFT_Init_SSD1963_8bit696: ;__Lib_TFT_Defs.mbas,3554 :: TFT_Set_Index_Ptr = @TFT_SSD1963_8bit_Set_Index LUI R2, hi_addr(_TFT_SSD1963_8bit_Set_Index+0) ORI R2, R2, lo_addr(_TFT_SSD1963_8bit_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3555 :: TFT_Write_Command_Ptr = @TFT_SSD1963YT_8bit_Write_Command LUI R2, hi_addr(_TFT_SSD1963YT_8bit_Write_Command+0) ORI R2, R2, lo_addr(_TFT_SSD1963YT_8bit_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3556 :: TFT_Write_Data_Ptr = @TFT_SSD1963_8bit_Write_Data LUI R2, hi_addr(_TFT_SSD1963_8bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_SSD1963_8bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_SSD1963_8bit428: ;__Lib_TFT_Defs.mbas,3559 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,3560 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,3561 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_SSD1963_8bit697 NOP J L__TFT_Init_SSD1963_8bit431 NOP L__TFT_Init_SSD1963_8bit697: ;__Lib_TFT_Defs.mbas,3562 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_SSD1963_8bit432 NOP ;__Lib_TFT_Defs.mbas,3563 :: else L__TFT_Init_SSD1963_8bit431: ;__Lib_TFT_Defs.mbas,3564 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,3565 :: end if L__TFT_Init_SSD1963_8bit432: ;__Lib_TFT_Defs.mbas,3567 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,3568 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,3570 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,3571 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,3573 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,3574 :: TFT_Reset_SSD1963_8bit() JAL __Lib_TFT_Defs_TFT_Reset_SSD1963_8bit+0 NOP ;__Lib_TFT_Defs.mbas,3575 :: TFT_SSD1963_Set_Address_Ptr = @TFT_Set_Address_SSD1963II LUI R2, hi_addr(_TFT_Set_Address_SSD1963II+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SSD1963II+0) SW R2, Offset(_TFT_SSD1963_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3576 :: end sub L_end_TFT_Init_SSD1963_8bit: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_SSD1963_8bit _TFT_Init_SSD1963_8bit_Custom: ;__Lib_TFT_Defs.mbas,3586 :: sub procedure TFT_Init_SSD1963_8bit_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3587 :: __controller = _8BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 255 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,3588 :: TFT_Set_SSD1963() JAL _TFT_Set_SSD1963+0 NOP ;__Lib_TFT_Defs.mbas,3589 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_SSD1963_8bit_Custom700 NOP J L__TFT_Init_SSD1963_8bit_Custom435 NOP L__TFT_Init_SSD1963_8bit_Custom700: ;__Lib_TFT_Defs.mbas,3590 :: TFT_Set_Index_Ptr = @TFT_SSD1963_8bit_Set_Index LUI R2, hi_addr(_TFT_SSD1963_8bit_Set_Index+0) ORI R2, R2, lo_addr(_TFT_SSD1963_8bit_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3591 :: TFT_Write_Command_Ptr = @TFT_SSD1963YT_8bit_Write_Command LUI R2, hi_addr(_TFT_SSD1963YT_8bit_Write_Command+0) ORI R2, R2, lo_addr(_TFT_SSD1963YT_8bit_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3592 :: TFT_Write_Data_Ptr = @TFT_SSD1963_8bit_Write_Data LUI R2, hi_addr(_TFT_SSD1963_8bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_SSD1963_8bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_SSD1963_8bit_Custom435: ;__Lib_TFT_Defs.mbas,3595 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,3596 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,3597 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_SSD1963_8bit_Custom701 NOP J L__TFT_Init_SSD1963_8bit_Custom438 NOP L__TFT_Init_SSD1963_8bit_Custom701: ;__Lib_TFT_Defs.mbas,3598 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_SSD1963_8bit_Custom439 NOP ;__Lib_TFT_Defs.mbas,3599 :: else L__TFT_Init_SSD1963_8bit_Custom438: ;__Lib_TFT_Defs.mbas,3600 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,3601 :: end if L__TFT_Init_SSD1963_8bit_Custom439: ;__Lib_TFT_Defs.mbas,3603 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,3604 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,3606 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,3607 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,3609 :: TFT_Reset_SSD1963_8bit() JAL __Lib_TFT_Defs_TFT_Reset_SSD1963_8bit+0 NOP ;__Lib_TFT_Defs.mbas,3610 :: TFT_SSD1963_Set_Address_Ptr = @TFT_Set_Address_SSD1963II LUI R2, hi_addr(_TFT_Set_Address_SSD1963II+0) ORI R2, R2, lo_addr(_TFT_Set_Address_SSD1963II+0) SW R2, Offset(_TFT_SSD1963_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3611 :: end sub L_end_TFT_Init_SSD1963_8bit_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_SSD1963_8bit_Custom _TFT_Init_HX8347G_16bit: ;__Lib_TFT_Defs.mbas,3620 :: sub procedure TFT_Init_HX8347G_16bit(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3621 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,3622 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_HX8347G_16bit704 NOP J L__TFT_Init_HX8347G_16bit442 NOP L__TFT_Init_HX8347G_16bit704: ;__Lib_TFT_Defs.mbas,3623 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3624 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3625 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_HX8347G_16bit442: ;__Lib_TFT_Defs.mbas,3628 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,3629 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,3630 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_HX8347G_16bit705 NOP J L__TFT_Init_HX8347G_16bit445 NOP L__TFT_Init_HX8347G_16bit705: ;__Lib_TFT_Defs.mbas,3631 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_HX8347G_16bit446 NOP ;__Lib_TFT_Defs.mbas,3632 :: else L__TFT_Init_HX8347G_16bit445: ;__Lib_TFT_Defs.mbas,3633 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,3634 :: end if L__TFT_Init_HX8347G_16bit446: ;__Lib_TFT_Defs.mbas,3636 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,3637 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,3639 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,3640 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,3641 :: TFT_Set_DataPort_Direction() JAL __Lib_TFT_Defs_TFT_Set_DataPort_Direction+0 NOP ;__Lib_TFT_Defs.mbas,3643 :: TFT_Reset_HX8347G() JAL __Lib_TFT_Defs_TFT_Reset_HX8347G+0 NOP ;__Lib_TFT_Defs.mbas,3644 :: TFT_Set_Address_Ptr = @TFT_Set_Address LUI R2, hi_addr(_TFT_Set_Address+0) ORI R2, R2, lo_addr(_TFT_Set_Address+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3645 :: end sub L_end_TFT_Init_HX8347G_16bit: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_HX8347G_16bit _TFT_Init_HX8347G_16bit_Custom: ;__Lib_TFT_Defs.mbas,3655 :: sub procedure TFT_Init_HX8347G_16bit_Custom(dim display_width as word display_height as word) ADDIU SP, SP, -20 SW RA, 0(SP) ;__Lib_TFT_Defs.mbas,3656 :: __controller = _16BIT_CONTROLLER SW R25, 4(SP) SW R26, 8(SP) SW R27, 12(SP) SW R28, 16(SP) ORI R2, R0, 65535 SH R2, Offset(__Lib_TFT_Defs___controller+0)(GP) ;__Lib_TFT_Defs.mbas,3657 :: if (Is_TFT_Set() <> 1) then JAL _Is_TFT_Set+0 NOP ANDI R3, R2, 255 ORI R2, R0, 1 BNE R3, R2, L__TFT_Init_HX8347G_16bit_Custom708 NOP J L__TFT_Init_HX8347G_16bit_Custom449 NOP L__TFT_Init_HX8347G_16bit_Custom708: ;__Lib_TFT_Defs.mbas,3658 :: TFT_Set_Index_Ptr = @TFT_Set_Index LUI R2, hi_addr(_TFT_Set_Index+0) ORI R2, R2, lo_addr(_TFT_Set_Index+0) SW R2, Offset(_TFT_Set_Index_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3659 :: TFT_Write_Command_Ptr = @TFT_Write_Command LUI R2, hi_addr(_TFT_Write_Command+0) ORI R2, R2, lo_addr(_TFT_Write_Command+0) SW R2, Offset(_TFT_Write_Command_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3660 :: TFT_Write_Data_Ptr = @TFT_16bit_Write_Data LUI R2, hi_addr(_TFT_16bit_Write_Data+0) ORI R2, R2, lo_addr(_TFT_16bit_Write_Data+0) SW R2, Offset(_TFT_Write_Data_Ptr+0)(GP) L__TFT_Init_HX8347G_16bit_Custom449: ;__Lib_TFT_Defs.mbas,3663 :: TFT_DISP_WIDTH = display_width SH R25, Offset(_TFT_DISP_WIDTH+0)(GP) ;__Lib_TFT_Defs.mbas,3664 :: TFT_DISP_HEIGHT = display_height SH R26, Offset(_TFT_DISP_HEIGHT+0)(GP) ;__Lib_TFT_Defs.mbas,3665 :: if (display_width >= display_height) then ANDI R3, R25, 65535 ANDI R2, R26, 65535 SLTU R2, R3, R2 BEQ R2, R0, L__TFT_Init_HX8347G_16bit_Custom709 NOP J L__TFT_Init_HX8347G_16bit_Custom452 NOP L__TFT_Init_HX8347G_16bit_Custom709: ;__Lib_TFT_Defs.mbas,3666 :: TFT_Disp_Rotation = 0 SB R0, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) J L__TFT_Init_HX8347G_16bit_Custom453 NOP ;__Lib_TFT_Defs.mbas,3667 :: else L__TFT_Init_HX8347G_16bit_Custom452: ;__Lib_TFT_Defs.mbas,3668 :: TFT_Disp_Rotation = 90 ORI R2, R0, 90 SB R2, Offset(__Lib_TFT_Defs_TFT_Disp_Rotation+0)(GP) ;__Lib_TFT_Defs.mbas,3669 :: end if L__TFT_Init_HX8347G_16bit_Custom453: ;__Lib_TFT_Defs.mbas,3671 :: TFT_Set_Pen(CL_BLACK, 1) ORI R26, R0, 1 MOVZ R25, R0, R0 JAL _TFT_Set_Pen+0 NOP ;__Lib_TFT_Defs.mbas,3672 :: TFT_Set_Brush(0, 0, 0, 0, 0, 0) MOVZ R28, R0, R0 MOVZ R27, R0, R0 MOVZ R26, R0, R0 MOVZ R25, R0, R0 ADDIU SP, SP, -4 SH R0, 2(SP) SH R0, 0(SP) JAL _TFT_Set_Brush+0 NOP ADDIU SP, SP, 4 ;__Lib_TFT_Defs.mbas,3674 :: TFT_Move_Cursor(0, 0) MOVZ R26, R0, R0 MOVZ R25, R0, R0 JAL _TFT_Move_Cursor+0 NOP ;__Lib_TFT_Defs.mbas,3675 :: TFT_Clear_Fonts() JAL _TFT_Clear_Fonts+0 NOP ;__Lib_TFT_Defs.mbas,3677 :: TFT_Reset_HX8347G() JAL __Lib_TFT_Defs_TFT_Reset_HX8347G+0 NOP ;__Lib_TFT_Defs.mbas,3678 :: TFT_Set_Address_Ptr = @TFT_Set_Address LUI R2, hi_addr(_TFT_Set_Address+0) ORI R2, R2, lo_addr(_TFT_Set_Address+0) SW R2, Offset(_TFT_Set_Address_Ptr+0)(GP) ;__Lib_TFT_Defs.mbas,3679 :: end sub L_end_TFT_Init_HX8347G_16bit_Custom: LW R28, 16(SP) LW R27, 12(SP) LW R26, 8(SP) LW R25, 4(SP) LW RA, 0(SP) ADDIU SP, SP, 20 JR RA NOP ; end of _TFT_Init_HX8347G_16bit_Custom