;VEVO4
;BNA
;2006.12.12.
;-----------------------------------------------------------------------------------
.include "m16def.inc"


;Tolerance
.equ	TOL=0x08		

;Init:
 
;Set Stack Pointer to 0x0080

	ldi 	r16,0x00
	ldi 	r17,0x80

	out 	SPH,r16
	out 	SPL,r17

	
;Init 16bit Timer/Counter
;Timer/Counter1 Control Registers
;Normal mode

;Timer Stopregister
	ldi		r30,0x00
	
	ldi		r19,0x00
	out 	TCCR1A,r19
	out 	TCCR1B,r19

;Timer Startregister	
	ldi		r31,0x02

;Port Initialisation
	
	;Port B kimenetre allitasa
	ldi 	r20,0xff
	out 	DDRB,r20
	

LOOP:

;***---Load Port D---*** 	
;PD2 = INT0
;low-active

	in		r20,PIND
	sbrs	r20,2
	call	RECEIVE

rjmp LOOP

RECEIVE:
;----------------------	
	;Global Interrupt Disable
	cli
	;r24 <- ide kerül majd a kód
	;Kinullázzuk
	ldi 	r24,0x00	

	;LEADER BURST 
	call 	SUB_M_LOW
	
	;9ms
	ldi 	r26,0x65
	ldi		r27,0x04
	
	;Check 9ms
	call	SUB_COMPARE
	cpi		r25,0x01
	brne	END_INT

	;LEADER SILENCE
	call	SUB_M_HIGH

	;4,5ms
	ldi		r26,0x33
	ldi		r27,0x02
	;Check	4,5ms
	call	SUB_COMPARE
	cpi		r25,0x01
	brne	END_INT
;-----------------------
	;r23 for ciklus számlálója
	;r23 nullázása
	ldi		r23,0x00

;*--------------*
DATA:


	;Bit7-0
	;Burst
	call	SUB_M_LOW
	
	;4ms
	ldi		r26,0xF4
	ldi		r27,0x01
	;Check	4ms	
	call	SUB_COMPARE
	sbrc	r25,0
	;STORE 1
	call	SUB_STORE_1
	
	sbrc	r25,0
	rjmp	Silence	

	;2ms	
	ldi		r26,0xFA
	ldi		r27,0x00
	;Check 	2ms
	call	SUB_COMPARE
	cpi		r25,0x01
	brne	END_INT
	;STORE 0
	call	SUB_STORE_0
	;End Burst	

Silence:
	
	call	SUB_M_HIGH

	;2ms	
	ldi		r26,0xFA
	ldi		r27,0x00
	;Check 	2ms
	call	SUB_COMPARE
	cpi		r25,0x01
	brne	END_INT
	
	;For ciklus
	inc		r23
	cpi		r23,0x08
	breq	CHECK
	rjmp	DATA

;-----------------------------------------------------------------------------------

END_INT:

	;RESET TIMER	(r30=0x00)
	out		TCNT1H,r30
	out		TCNT1L,r30

	;MOTOR STOP
	out		PORTB,r30

	;Global Interrupt Enable
	sei

reti
;-----------------------------------------------------------------------------------

CHECK:

	mov		r20,r24
	;Copy 	r24 -> r23
	mov 	r23,r24
	
	;4x logical shift left in r23
	lsl		r23
	lsl		r23
	lsl		r23
	lsl 	r23
	
	;invert r23
	com		r23

	;Mask High bits of r23 & r24
	andi	r23,0xF0
	andi	r24,0xF0
	
	;Compare r28 with r29
	cp		r23,r24
	brne	END_INT
		
	;EXOR Elore-Hatra es EXOR Balra-Jobbra
	
	sbrc	r24,7
	andi 	r24,0b10111111
	
	sbrc	r24,6
	andi	r24,0b01111111

	sbrc	r24,5
	andi	r24,0b11101111

	sbrc	r24,4
	andi	r24,0b11011111

MOTOR_CONTROL:

	;Előre=?
	sbrc	r24,7
	ldi		r22,0x01
	
	;Hátra=?
	sbrc	r24,6
	ldi		r22,0x02
	
	;Kiküldi a motornak
	out		PORTB,r22
	
	;Kilepes
	rjmp END_INT

;-----------------------------------------------------------------------------------
SUB_M_LOW:
;***Return Value in r28-r29***
	
	;Reset Timer
	out		TCNT1H,r30
	out		TCNT1L,r30

	;Start Timer
	out 	TCCR1B,r31

READ_LOW:
	
	in 		r16,PIND

	sbrs	r16,2
	rjmp	READ_LOW

	;Stop Timer
	out 	TCCR1B,r30

	;Load Timer Value to r28-29 register-pairs
	
	in		r28,TCNT1L
	in 		r29,TCNT1H

ret

;-----------------------------------------------------------------------------------

SUB_M_HIGH:
;***Return Value in r28-r29***
	
	;Reset Timer
	out		TCNT1H,r30
	out		TCNT1L,r30

	;Start Timer
	out 	TCCR1B,r31

READ_HIGH:
	
	in 		r16,PIND

	sbrc	r16,2
	rjmp	READ_HIGH

	;Stop Timer
	out 	TCCR1B,r30

	;Load Timer Value to r28-29 register-pairs
	
	in		r28,TCNT1L
	in 		r29,TCNT1H

ret

SUB_COMPARE:
;Input r26-r27  <-  Base value
;Return r25(0 bit)

	ldi 	r25,0x00
	
	cpse	r27,r29
	rjmp	HIGH_VIZSGALAT
	
	cpse	r26,r28
	rjmp	LOW_VIZSGALAT
	
	rjmp	END_COMP_OK
		
HIGH_VIZSGALAT:
	
	cp		r27,r29
	brmi	NAGYOBB	;Nagyobb mint a base

KISEBB:
;mert kisebb mint a base
	
	adiw	r28,TOL
	
	cp		r29,r27
	brmi	END_COMP
	
	cp		r28,r26
	brmi	END_COMP
	
	rjmp	END_COMP_OK	

NAGYOBB:
;mert nagyobb mint a base
	
	adiw	r26,TOL
	
	cp		r27,r29
	brmi	END_COMP
	
	cp		r26,r28
	brmi	END_COMP
	
	rjmp	END_COMP_OK	

LOW_VIZSGALAT:
		
	cp		r26,r28
	brmi	NAGYOBB	;Nagyobb mint a base
	brpl	KISEBB

END_COMP_OK:
	
	ldi		r25,0x01

END_COMP:

ret

SUB_STORE_1:
;Store 1 to r24 register 0bit and shift left
;Return	r24 register
	
	ori		r24,0x01
	cpi		r23,0x07
	;Utolsónál nem kell shiftelni!
	breq	END_STORE_1	

	lsl		r24

	END_STORE_1:

ret

SUB_STORE_0:
;Store 0 to r24 register 0bit and shift left
;Return r24 register
	
	cpi		r23,0x07
	;Utolsónál nem kell shiftelni!
	breq	END_STORE_0	
	
	lsl		r24

	END_STORE_0:

ret
