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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:38:44 10/16/2009 
-- Design Name: 
-- Module Name:    counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
    Port ( sw0 : in  STD_LOGIC;
           sw1 : in  STD_LOGIC;
           Q : out  STD_LOGIC_VECTOR (7 downto 0);
           CLK : in  STD_LOGIC);
end counter;

architecture Behavioral of counter is
	
signal sCLK, ssw0, ssw1 : STD_LOGIC;
signal sQ : STD_LOGIC_VECTOR ( 7 downto 0 ):=X"0F";

begin
sCLK<=CLK;
ssw0<=sw0;
ssw1<=sw1;
	process(sCLK)
	variable vcnt : integer range 0 to 2000001;
	variable vst : integer;
	begin
		
		if vcnt=2000000 then
			vcnt:=0;
			if vst=-1 then
				vst:=0;
				sQ<= X"FF";
			else 
				vst:=-1;
				sQ<= X"00";
			end if;
		end if;
		
		vcnt:=vcnt+1;
		
		--if( vst=true ) then
		--	sQ<=X"FF";-- not sQ;
		--else
		--	sQ<=X"00";
		--end if;
		
		--if( ssw0='1' ) then 
		--vst:= not vst;
		--end if;
		
		Q<=sQ;
		--wait sCLK;
	end process;
end Behavioral;